Re: [Gems-users] LogTM Transactions Hanging (Gems 2.1)

["Fuad Tabba" <fuad@xxxxxxxxxxxxxxxxx>]

Thanks Javier and Jayaram.

Now I'm going to ask what might seem obvious; what do I do about it?
How do I use instruction-cache-access-trace with a line size equal to
the instruction size, or how do I _not_ use
instruction-cache-access-trace to begin with?

Also, why am I using instruction-cache-access-trace? All I did was
install simics and gems by following the documentation on the gems
website, so how come it's different from what you (I'm assuming) are
using?

Thanks again.

Cheers,
/Fuad


On Thu, Jun 19, 2008 at 10:08 AM, Jayaram Bobba <bobba@xxxxxxxxxxx> wrote:
> Thanks Javier for the clarification. I believe that instruction-fetch-mode
> could influence the correctness of the simulation. Some conflict resolution
> policies (like Timestamp) require the simulator to see every instruction
> fetch.
> Typically, once a transaction is marked as 'to be aborted' by the
> conflict resolution policy,
> the simulator generates a trap on the next memory request it receives
> from SIMICS. Now if
> the next instruction happens to be COMMIT_TRANSACTION and SIMICS does not
> report every instruction fetch then the transaction could be incorrectly
> committed.
>
> So if you need to use instruction-cache-access-trace, then you should
> use it with a line
> size equal to the instruction size.
>
>
> Javier Merino wrote:
>> Fuad Tabba wrote:
>>
>>>> I am not sure what instruction-cache-access-trace is and how it differs
>>>> from instruction-fetch-trace. The difference
>>>> if any could also affect trap handling.
>>>>
>>> Not really sure how why it is instruction-cache-access-trace as
>>> opposed to instruction-fetch-trace. Is there a parameter I could
>>> change?
>>>
>>>
>>
>> From the serengeti reference manual:
>> "If [instruction-fetch-mode is] set to instruction-cache-access-trace,
>> the memory hierarchy will receive one (and only one) instruction fetch
>> every time a new cache line is accessed. [...] If set to
>> instruction-fetch-trace, all instruction fetches will be visible. Note
>> that on x86 target, instruction-cache-trace-access is not available. On
>> some other, instruction-fetch-trace is actually
>> instruction-cache-trace-access with a line size equal to
>> the instruction size (sparc-v9)."
>>
>> Simics warns you that instruction-fetch-mode is using
>> instruction-cache-access-trace. It is ok, I don't think that's the
>> source of your problem.
>>
>> Regards,
>> Javier Merino
>>
>>
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>>
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