Fuad Tabba wrote:
I am not sure what instruction-cache-access-trace is and how it differs
from instruction-fetch-trace. The difference
if any could also affect trap handling.
Not really sure how why it is instruction-cache-access-trace as
opposed to instruction-fetch-trace. Is there a parameter I could
change?
From the serengeti reference manual:
"If [instruction-fetch-mode is] set to instruction-cache-access-trace,
the memory hierarchy will receive one (and only one) instruction fetch
every time a new cache line is accessed. [...] If set to
instruction-fetch-trace, all instruction fetches will be visible. Note
that on x86 target, instruction-cache-trace-access is not available. On
some other, instruction-fetch-trace is actually
instruction-cache-trace-access with a line size equal to
the instruction size (sparc-v9)."
Simics warns you that instruction-fetch-mode is using
instruction-cache-access-trace. It is ok, I don't think that's the
source of your problem.
Regards,
Javier Merino
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