Branch: refs/heads/angushe/riscv
Home: https://github.com/dyninst/dyninst
Commit: b802478e52d9b0d2856a09f2412035a0efa87640
https://github.com/dyninst/dyninst/commit/b802478e52d9b0d2856a09f2412035a0efa87640
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M CMakeLists.txt
A cmake/tpls/DyninstCapstone.cmake
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Add CMake stub
Commit: 2cb98c3340d706ca25bb52a761b0455671c5e01c
https://github.com/dyninst/dyninst/commit/2cb98c3340d706ca25bb52a761b0455671c5e01c
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A instructionAPI/capstone/import.py
A instructionAPI/capstone/x86.py
Log Message:
-----------
Make parameter the root directory in import script
Instead of specifying the file name, the user just points to the
directory and the script will grab the necessary files.
Commit: 6246b654b8a12f4f08cd60de485344be24b5f7ec
https://github.com/dyninst/dyninst/commit/6246b654b8a12f4f08cd60de485344be24b5f7ec
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/capstone/import.py
M instructionAPI/capstone/x86.py
Log Message:
-----------
Alias faddp to fadd
Capstone only uses fadd. This does not modify the entryIDs yet.
Commit: 48f2d93e9770a842f8095ddf6af7fc8c345060e4
https://github.com/dyninst/dyninst/commit/48f2d93e9770a842f8095ddf6af7fc8c345060e4
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/capstone/import.py
Log Message:
-----------
Add mnemonic translation to import script
Commit: e2f46b98cbc707ffbc8342ab98956a27091252bd
https://github.com/dyninst/dyninst/commit/e2f46b98cbc707ffbc8342ab98956a27091252bd
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A instructionAPI/src/x86/register-xlat.C
A instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
Add Capstone->Dyninst register translation
Commit: 9c6ab8cc398c5490e7c379108a2a324265a9625e
https://github.com/dyninst/dyninst/commit/9c6ab8cc398c5490e7c379108a2a324265a9625e
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A instructionAPI/src/x86/mnemonic-xlat.C
A instructionAPI/src/x86/mnemonic-xlat.h
Log Message:
-----------
Add Capstone->Dyninst mnemonic translation
Commit: 6f6538d86ca0f55110ff6cabde349f2da9b95d15
https://github.com/dyninst/dyninst/commit/6f6538d86ca0f55110ff6cabde349f2da9b95d15
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
A instructionAPI/src/x86/decoder.C
A instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add stub replacement for x86 decoder
Commit: 55eee8efae25b43d8806a5f59f993365dcbd0aa3
https://github.com/dyninst/dyninst/commit/55eee8efae25b43d8806a5f59f993365dcbd0aa3
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add decoder ctor and dtor
There is one usage of Capstone per decoder. This should be threadsafe
as it doesn't make sense to use a decoder with multiple threads
simultaneously. See comments in ctor for why there are two Capstone
handles per decoder.
Commit: 58c37dee4ab8f89549334fddbf04747942196075
https://github.com/dyninst/dyninst/commit/58c37dee4ab8f89549334fddbf04747942196075
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add decodeOpcode
Commit: 66e4ebb6b64d5dddaeece7ce879371893afd6e5e
https://github.com/dyninst/dyninst/commit/66e4ebb6b64d5dddaeece7ce879371893afd6e5e
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add note in decodeOperands
Commit: 48d33ebf4371b7cc7fc2df8c59d50a3eb46d30f7
https://github.com/dyninst/dyninst/commit/48d33ebf4371b7cc7fc2df8c59d50a3eb46d30f7
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add doDelayedDecode
This is a copy/paste of Xiaozhu's implementation. It appears to be
incomplete (as per the comments).
Commit: 0962f1b2887c393171d51fc0de9b8b6a915e0f94
https://github.com/dyninst/dyninst/commit/0962f1b2887c393171d51fc0de9b8b6a915e0f94
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
stub -- refactor
Commit: cf1ddb403d7c2b64f305f6cbf3a52606f77566c5
https://github.com/dyninst/dyninst/commit/cf1ddb403d7c2b64f305f6cbf3a52606f77566c5
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Use disassembler object in decode_operands
Commit: f881140f82dddf21a06b53b489e3a77c571925cf
https://github.com/dyninst/dyninst/commit/f881140f82dddf21a06b53b489e3a77c571925cf
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Refactor decode_operands
This makes it much easier to follow.
Commit: 6a0692499891140e04f7a76d6f3b23f494585773
https://github.com/dyninst/dyninst/commit/6a0692499891140e04f7a76d6f3b23f494585773
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add detailed comments about operand types
Commit: 6f4f0fa9eca820912ee8967cb2898ad8ece47a82
https://github.com/dyninst/dyninst/commit/6f4f0fa9eca820912ee8967cb2898ad8ece47a82
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use Instruction::makeReturnExpression
No need to reinvent the wheel.
Commit: 418c87d94c2a3334ec53dcddc93116261dc7e255
https://github.com/dyninst/dyninst/commit/418c87d94c2a3334ec53dcddc93116261dc7e255
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove redundant includes
Commit: 3160907edbda7dfe9774044e99ec3c468c1017d8
https://github.com/dyninst/dyninst/commit/3160907edbda7dfe9774044e99ec3c468c1017d8
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor handling of implicit registers
By giving the properties names rather than std::pairs, it makes it much
easier to read.
Commit: 5134c7e55e37ed1599bc261daaae5602fa6e999c
https://github.com/dyninst/dyninst/commit/5134c7e55e37ed1599bc261daaae5602fa6e999c
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Include decoding of {e,r}flags
Commit: 09f56e27ba15035cae070915631b3b9fa1059f21
https://github.com/dyninst/dyninst/commit/09f56e27ba15035cae070915631b3b9fa1059f21
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment for explicit operands
Commit: 3d51fc567878354ee776986765dd342ac7eaff38
https://github.com/dyninst/dyninst/commit/3d51fc567878354ee776986765dd342ac7eaff38
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix explicit operands example
Commit: ecd9b1a0e58050b742f148372425efe8f618c2ee
https://github.com/dyninst/dyninst/commit/ecd9b1a0e58050b742f148372425efe8f618c2ee
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove extraneous namespace qualifier
Commit: 65b884768e7a7df42205c1b9214421852907dc8b
https://github.com/dyninst/dyninst/commit/65b884768e7a7df42205c1b9214421852907dc8b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor is_call
The original code did the nested check, but didn't need to.
if(cat == c_BranchInsn || cat == c_CallInsn) {
isCFT = true;
if(cat == c_CallInsn) {
isCall = true;
}
}
is equivalent to
if(cat == c_CallInsn) {
isCall = true;
}
if(cat == c_BranchInsn || isCall) {
isCFT = true;
}
Commit: fefbed24fdf2dd9bc4e2b344cb7d90beaddeb1d5
https://github.com/dyninst/dyninst/commit/fefbed24fdf2dd9bc4e2b344cb7d90beaddeb1d5
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment in expand_eflags
Commit: dcc57e37ad1e83bcd871b0d25de5b4edbe0fc480
https://github.com/dyninst/dyninst/commit/dcc57e37ad1e83bcd871b0d25de5b4edbe0fc480
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/register-xlat.C
Log Message:
-----------
Fix comment for BND registers
Commit: 2a11cf472fbea9787a8f500a20e3da501ed8d82b
https://github.com/dyninst/dyninst/commit/2a11cf472fbea9787a8f500a20e3da501ed8d82b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_reg
Commit: 9e24b677e4e3ccf69f46f0a8f40d84248778da11
https://github.com/dyninst/dyninst/commit/9e24b677e4e3ccf69f46f0a8f40d84248778da11
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_imm
Commit: ba38d4e16378e73ca52d593b3f0a113d44ccc8a6
https://github.com/dyninst/dyninst/commit/ba38d4e16378e73ca52d593b3f0a113d44ccc8a6
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed 64-bit values for immediates
Commit: b5f9e297eb4fe239863364239ee1eefa47968b2b
https://github.com/dyninst/dyninst/commit/b5f9e297eb4fe239863364239ee1eefa47968b2b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Update comment for relative branch immediates
Commit: 8d9d3d5969e2bc9aba2d937753c97fec201b0681
https://github.com/dyninst/dyninst/commit/8d9d3d5969e2bc9aba2d937753c97fec201b0681
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove error check on size_to_type
It has been updated to include all values used by Capstone.
Commit: 7c919d3751e3fb1752226c5894d0124e2e3be048
https://github.com/dyninst/dyninst/commit/7c919d3751e3fb1752226c5894d0124e2e3be048
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove unneeded assert
Commit: 5b608e1a0bc557c76cf05289a40547482e12d945
https://github.com/dyninst/dyninst/commit/5b608e1a0bc557c76cf05289a40547482e12d945
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move is_call and is_cft to where they are used
Commit: 96c0dcc48056b8e5c4553045c4af42187582fff3
https://github.com/dyninst/dyninst/commit/96c0dcc48056b8e5c4553045c4af42187582fff3
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed values for calculations
The manual says everything but the scale can be positive or negative.
Commit: 1c8dd5bf1dfb32c797236b5145a8f72d532f69e9
https://github.com/dyninst/dyninst/commit/1c8dd5bf1dfb32c797236b5145a8f72d532f69e9
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use braces
Commit: 193da59209a0367aea454be24c247f6f37b49e35
https://github.com/dyninst/dyninst/commit/193da59209a0367aea454be24c247f6f37b49e35
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move size_to_type to where it is used
Commit: b4bac7cf0b8cba0682dd5c47cd1a3df17c5c7b33
https://github.com/dyninst/dyninst/commit/b4bac7cf0b8cba0682dd5c47cd1a3df17c5c7b33
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add some whitespace
Commit: 53526c1c8aec8d19cbaddffd62e41a8ba56ffc80
https://github.com/dyninst/dyninst/commit/53526c1c8aec8d19cbaddffd62e41a8ba56ffc80
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add description from Intel manual
Commit: 4e660becde4536a045fca5273123bfc20c4a3e93
https://github.com/dyninst/dyninst/commit/4e660becde4536a045fca5273123bfc20c4a3e93
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Return early if processing a CFT
Commit: 807a2aee339541490465ca46a5f73055cede38d2
https://github.com/dyninst/dyninst/commit/807a2aee339541490465ca46a5f73055cede38d2
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add comment about LEA
Commit: d12d8866c16fe64888c9755bf2f17d6467a42a0b
https://github.com/dyninst/dyninst/commit/d12d8866c16fe64888c9755bf2f17d6467a42a0b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Rename immAST -> displacementAST
This better reflects its meaning.
Commit: f02325ebaaa04c8d101988314fede1c7ae43d6a0
https://github.com/dyninst/dyninst/commit/f02325ebaaa04c8d101988314fede1c7ae43d6a0
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Handle segment registers as memory operands
Commit: 75cfb53abc23dff2f9e793c9ddbd74e6ae5c02d2
https://github.com/dyninst/dyninst/commit/75cfb53abc23dff2f9e793c9ddbd74e6ae5c02d2
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Fix cmake formatting in instructionAPI/CMakeLists.txt
Commit: 91d7f836fe41e872b4f9f11f9a4dc2a77ec7e77f
https://github.com/dyninst/dyninst/commit/91d7f836fe41e872b4f9f11f9a4dc2a77ec7e77f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M .github/workflows/dependency-version.yaml
M docker/dependencies.versions
Log Message:
-----------
Add dependency-version check for Capstone
Commit: da2f6fad6f0530fb6edf533af6437fe85236a10d
https://github.com/dyninst/dyninst/commit/da2f6fad6f0530fb6edf533af6437fe85236a10d
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Make Capstone a private dependency
Commit: e10cfdcf7eeed2d5b36204bb6ed85e8637ef9a54
https://github.com/dyninst/dyninst/commit/e10cfdcf7eeed2d5b36204bb6ed85e8637ef9a54
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A docker/build_capstone.sh
M docker/dependencies.versions
Log Message:
-----------
Docker: add Capstone builds
Commit: 3823c8d0eaa13ecea995c9c82124721abc11a89f
https://github.com/dyninst/dyninst/commit/3823c8d0eaa13ecea995c9c82124721abc11a89f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Only decode segment register operands for i386
Commit: f90af34600e2ad43f014b0427dfa577a6955d9e5
https://github.com/dyninst/dyninst/commit/f90af34600e2ad43f014b0427dfa577a6955d9e5
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix format from clang's -Wformat-pedantic
Commit: 4cb1b59e5d8b0f20d9fa5274fc3ce893802f82a0
https://github.com/dyninst/dyninst/commit/4cb1b59e5d8b0f20d9fa5274fc3ce893802f82a0
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M cmake/tpls/DyninstCapstone.cmake
Log Message:
-----------
Use correct capitalization for capstone_ROOT in CMake
Commit: 9022d2e291310a76ac47989d2ab675e53700f414
https://github.com/dyninst/dyninst/commit/9022d2e291310a76ac47989d2ab675e53700f414
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/h/Architecture.h
M dwarf/src/dwarfHandle.C
Log Message:
-----------
Add riscv architecture
Commit: 5afe8054c53a1e5732832b62235f7e9551cfc02e
https://github.com/dyninst/dyninst/commit/5afe8054c53a1e5732832b62235f7e9551cfc02e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A instructionAPI/capstone/capstone.py
M instructionAPI/capstone/import.py
A instructionAPI/capstone/riscv64.py
Log Message:
-----------
Add riscv64 capstone parser
Commit: 1cecd96d3473bd976e4b1ffda7650d8c38ef55f5
https://github.com/dyninst/dyninst/commit/1cecd96d3473bd976e4b1ffda7650d8c38ef55f5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/CMakeLists.txt
M common/h/dyn_regs.h
M common/h/entryIDs.h
A common/h/mnemonics/riscv64_entryIDs.h
A common/h/registers/riscv64_regs.h
A common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add RISC-V registers and mnemonics
Commit: 6330a6430ad2299dba0e7fc3def1b60eccd5277e
https://github.com/dyninst/dyninst/commit/6330a6430ad2299dba0e7fc3def1b60eccd5277e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M elf/src/Elf_X.C
M proccontrol/src/process.C
Log Message:
-----------
Add cases for Arch_riscv64 to suppress compiler warnings
Commit: 25fa5df7cd7702f168fb964c2487d165d6bedb58
https://github.com/dyninst/dyninst/commit/25fa5df7cd7702f168fb964c2487d165d6bedb58
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
M instructionAPI/capstone/import.py
M instructionAPI/h/ArchSpecificFormatters.h
M instructionAPI/src/ArchSpecificFormatters.C
A instructionAPI/src/InstructionDecoder-Capstone.C
A instructionAPI/src/InstructionDecoder-Capstone.h
A instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/InstructionDecoderImpl.C
Log Message:
-----------
Add Capstone-based RISC-V InstructionAPI
Commit: 245c37edc514c1f34fd69bb43fcce2b5b9ec361b
https://github.com/dyninst/dyninst/commit/245c37edc514c1f34fd69bb43fcce2b5b9ec361b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M parseAPI/CMakeLists.txt
M parseAPI/src/CodeSource.C
M parseAPI/src/IA_IAPI.C
A parseAPI/src/IA_riscv64.C
A parseAPI/src/IA_riscv64.h
M parseAPI/src/SymbolicExpression.C
Log Message:
-----------
Add RISC-V ParseAPI
Commit: 4c646caf8e9c8b51f898b717f090b20c847cbd57
https://github.com/dyninst/dyninst/commit/4c646caf8e9c8b51f898b717f090b20c847cbd57
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A dataflowAPI/rose/SgAsmRiscv64Instruction.h
M dataflowAPI/rose/conversions.h
A dataflowAPI/rose/semantics/DispatcherRiscv64.C
A dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/Registers.h
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/RoseImpl.C
M dataflowAPI/src/RoseInsnFactory.C
M dataflowAPI/src/RoseInsnFactory.h
M dataflowAPI/src/SymEval.C
M dataflowAPI/src/SymbolicExpansion.C
M dataflowAPI/src/SymbolicExpansion.h
M dataflowAPI/src/convertOpcodes.C
A external/rose/riscv64InstructionEnum.h
M external/rose/rose-compat.h
Log Message:
-----------
Implement RISC-V DataflowAPI base code
Commit: ba520693bc71416fe27bddd24f95c4349f4e02dd
https://github.com/dyninst/dyninst/commit/ba520693bc71416fe27bddd24f95c4349f4e02dd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A dataflowAPI/sail/riscv_sail_to_rose.pl
A dataflowAPI/sail/sail_ast.pl
A dataflowAPI/sail/sail_lex.pl
A dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add sail lexical parser
Commit: fcc6259459fd259a4f56fcca02f0db66ec4b134d
https://github.com/dyninst/dyninst/commit/fcc6259459fd259a4f56fcca02f0db66ec4b134d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
rewrite sail lexer using regex
Commit: 375f27d7379ea961adc95c008248e9d65b71612b
https://github.com/dyninst/dyninst/commit/375f27d7379ea961adc95c008248e9d65b71612b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
Use array instead of hash
Commit: 4b2a40ffd0f360f65c2278cc51d2f22d3be8d081
https://github.com/dyninst/dyninst/commit/4b2a40ffd0f360f65c2278cc51d2f22d3be8d081
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add most syntax
Commit: 6735a2ae4cc9ec28b892c2de18f09eea32ea9bfc
https://github.com/dyninst/dyninst/commit/6735a2ae4cc9ec28b892c2de18f09eea32ea9bfc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A dataflowAPI/sail/riscv_ast.json
R dataflowAPI/sail/riscv_sail_to_rose.pl
R dataflowAPI/sail/sail_ast.pl
R dataflowAPI/sail/sail_lex.pl
R dataflowAPI/sail/sail_syntax.pl
A dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (UTYPE)
Commit: 489f590183bef6d64b37a3cacf9167a63b123d76
https://github.com/dyninst/dyninst/commit/489f590183bef6d64b37a3cacf9167a63b123d76
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/h/Architecture.h
Log Message:
-----------
Add missing riscv64 address width
Commit: b4e019348555bac3369a45dc456dc71a37f295fd
https://github.com/dyninst/dyninst/commit/b4e019348555bac3369a45dc456dc71a37f295fd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (IMAC subsets)
Commit: 8833864eee317ce9be5fbf0f49ec412bb9c7ca6a
https://github.com/dyninst/dyninst/commit/8833864eee317ce9be5fbf0f49ec412bb9c7ca6a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/src/ExpressionConversionVisitor.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Integrate riscv64 ROSE code into dataflowAPI
Commit: 4508880b3bc0ad0935da5cab8292b87f157cb6e5
https://github.com/dyninst/dyninst/commit/4508880b3bc0ad0935da5cab8292b87f157cb6e5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
R instructionAPI/src/x86/decoder.C
R instructionAPI/src/x86/decoder.h
R instructionAPI/src/x86/mnemonic-xlat.C
R instructionAPI/src/x86/mnemonic-xlat.h
R instructionAPI/src/x86/register-xlat.C
R instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
migrate instructionAPI to capstone
Commit: eed31d2ac58aa313d00ba28e1693b175ce0d24e6
https://github.com/dyninst/dyninst/commit/eed31d2ac58aa313d00ba28e1693b175ce0d24e6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/BaseSemantics2.h
A dataflowAPI/rose/semantics/ConcreteSemantics2.C
A dataflowAPI/rose/semantics/ConcreteSemantics2.h
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/SymEvalPolicy.h
Log Message:
-----------
fix mulhsu instruction semantic
Commit: 87cd5f7f0188415436e250a903605718ba6a5f2b
https://github.com/dyninst/dyninst/commit/87cd5f7f0188415436e250a903605718ba6a5f2b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M cmake/DyninstPlatform.cmake
M cmake/tpls/DyninstCapstone.cmake
M common/CMakeLists.txt
A common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M common/src/util.C
M dataflowAPI/src/ABI.C
M dataflowAPI/src/RegisterMap.C
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
A dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget.h
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
A dyninstAPI/src/codegen-riscv64.C
A dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.h
A dyninstAPI/src/emit-riscv64.C
A dyninstAPI/src/emit-riscv64.h
A dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/inst-riscv64.h
A dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/mapped_object.C
A dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI/src/unix.C
M dyninstAPI_RT/CMakeLists.txt
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/CMakeLists.txt
M proccontrol/src/linux.C
M proccontrol/src/linux.h
A proccontrol/src/loadLibrary/codegen-riscv64.C
M proccontrol/src/loadLibrary/codegen.C
M proccontrol/src/loadLibrary/codegen.h
A proccontrol/src/riscv_process.C
A proccontrol/src/riscv_process.h
Log Message:
-----------
Add RISC-V guards
Commit: 5fd703e33992104e4dff263da8811eb48432b2f3
https://github.com/dyninst/dyninst/commit/5fd703e33992104e4dff263da8811eb48432b2f3
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/binaryEdit.C
M dyninstAPI/src/codegen.C
M dyninstAPI/src/function.h
M dyninstAPI/src/linux.C
M stackwalk/CMakeLists.txt
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/framestepper.C
A stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/linux-swk.C
A stackwalk/src/riscv64-swk.C
A stackwalk/src/riscv64-swk.h
M symtabAPI/CMakeLists.txt
M symtabAPI/src/emitElfStatic.C
Log Message:
-----------
Add RISC-V stackwalk guard
Commit: beb5ee9fed3348f29feb2f773ff4ccc1f5db9e45
https://github.com/dyninst/dyninst/commit/beb5ee9fed3348f29feb2f773ff4ccc1f5db9e45
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A dyninstAPI_RT/src/RTthread-riscv64.c
Log Message:
-----------
Add missing RTthread-riscv64.c
Commit: 85cd30286c08155df91e50b531259839885c5ccc
https://github.com/dyninst/dyninst/commit/85cd30286c08155df91e50b531259839885c5ccc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A symtabAPI/src/emitElfStatic-riscv64.C
A symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Create RISC-V emitter template
Commit: a88717ff238b873ccff5fa762d57f47238291727
https://github.com/dyninst/dyninst/commit/a88717ff238b873ccff5fa762d57f47238291727
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A dyninstAPI_RT/src/RTstatic_ctors_dtors-riscv64.c
Log Message:
-----------
Add missing RTstatic_ctors_dtors-riscv64.c
Commit: 2d264e60e0bad33384a067cf54604a9237b6ea53
https://github.com/dyninst/dyninst/commit/2d264e60e0bad33384a067cf54604a9237b6ea53
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M common/src/dyninst_filesystem.h
M dataflowAPI/src/RegisterMap.h
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/RegisterConversion-riscv64.C
A dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
A dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/linux-riscv64.C
A dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.h
A dyninstAPI/src/stackwalk-riscv64.C
M dyninstAPI/src/unix.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
M symtabAPI/src/emitElfStatic-stub.C
Log Message:
-----------
Make RISC-V dyninst compile on a RISC-V machine
Commit: 851e8542ae2bf540078cc5b8a29cc7e5c9a3834b
https://github.com/dyninst/dyninst/commit/851e8542ae2bf540078cc5b8a29cc7e5c9a3834b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
M dyninstAPI/src/linux-riscv64.C
M dyninstAPI/src/parse-riscv64.C
Log Message:
-----------
Implement some instruction emission functions
Commit: 71a12221012841ec2ddf0305862e466e9ad76158
https://github.com/dyninst/dyninst/commit/71a12221012841ec2ddf0305862e466e9ad76158
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/registerSpace.h
M external/rose/riscv64InstructionEnum.h
Log Message:
-----------
Amalgamate 32 and 64 bit fpr
Commit: 8270d6125b31446131c3d6855c0855fdecb9351d
https://github.com/dyninst/dyninst/commit/8270d6125b31446131c3d6855c0855fdecb9351d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Add emitImm
Commit: c8aa05b77d830b9dd004b50d44624f3399614014
https://github.com/dyninst/dyninst/commit/c8aa05b77d830b9dd004b50d44624f3399614014
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/src/ABI.C
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/src/linux.C
M stackwalk/src/dbginfo-stepper.C
Log Message:
-----------
Rename arch_riscv64 to DYNINST_HOST_ARCH_AARCH64
Commit: fcf76f3fceaef2d7b550ab94b0f9fcb864d53e8a
https://github.com/dyninst/dyninst/commit/fcf76f3fceaef2d7b550ab94b0f9fcb864d53e8a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/CMakeLists.txt
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/convert.C
A dataflowAPI/rose/registers/riscv64.h
M dataflowAPI/src/convertOpcodes.C
M dwarf/CMakeLists.txt
M dwarf/src/registers/convert.C
A dwarf/src/registers/riscv64.h
M dyninstAPI/src/inst-riscv64.h
M external/rose/riscv64InstructionEnum.h
M parseAPI/CMakeLists.txt
Log Message:
-----------
Add missing RISC-V ROSE register conversion
Commit: 6a712d969055654c4a54e3a97c27fdf8200908f5
https://github.com/dyninst/dyninst/commit/6a712d969055654c4a54e3a97c27fdf8200908f5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/Instruction.C
Log Message:
-----------
Add missing invalid operand check
Commit: 395562c7d1073816ee7c2a7e6efa5ed23b81752d
https://github.com/dyninst/dyninst/commit/395562c7d1073816ee7c2a7e6efa5ed23b81752d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/riscv64.h
M dataflowAPI/src/RoseInsnFactory.h
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/mapped_object.C
M instructionAPI/h/Instruction.h
M instructionAPI/src/InstructionDecoder-Capstone.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/interrupts.C
M instructionAPI/src/syscalls.C
M parseAPI/CMakeLists.txt
M parseAPI/src/IA_riscv64.C
M stackwalk/CMakeLists.txt
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
M symtabAPI/CMakeLists.txt
Log Message:
-----------
Modify RISC-V Capstone instruction decoder
Commit: 81614b8113905cbb6eae790a9b89d6895376f9f6
https://github.com/dyninst/dyninst/commit/81614b8113905cbb6eae790a9b89d6895376f9f6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Add C-Type Emitter
Commit: 8dce4390be93e9b4cf02efc33c021a562c70b003
https://github.com/dyninst/dyninst/commit/8dce4390be93e9b4cf02efc33c021a562c70b003
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add Load Immediate
Commit: 5b93e2196aba9fba91da1d92661c67cf76eddda7
https://github.com/dyninst/dyninst/commit/5b93e2196aba9fba91da1d92661c67cf76eddda7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Change insn_size to is_compressed
Commit: cd3e4600c813c3e23e36429e5cbedc1ad9f6b97e
https://github.com/dyninst/dyninst/commit/cd3e4600c813c3e23e36429e5cbedc1ad9f6b97e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add addi codegen
Commit: 32a78f9eed59c082a1e5f0026b8d00af875e7af1
https://github.com/dyninst/dyninst/commit/32a78f9eed59c082a1e5f0026b8d00af875e7af1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Optimize addi Code Generation
Commit: 0ca295fcaddd422ab273d3ed1ad161f27993390a
https://github.com/dyninst/dyninst/commit/0ca295fcaddd422ab273d3ed1ad161f27993390a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M dyninstAPI/CMakeLists.txt
M dyninstAPI_RT/CMakeLists.txt
Log Message:
-----------
Fix DYNINST_ARCH_riscv64
Commit: d83c78db6e9bf13b39aaffbad99796ab95d07ced
https://github.com/dyninst/dyninst/commit/d83c78db6e9bf13b39aaffbad99796ab95d07ced
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/src/ABI.C
Log Message:
-----------
Add RISC-V initialize64
Commit: 7d7ccf81da1b9911f344310ac9d46f7b870c93fd
https://github.com/dyninst/dyninst/commit/7d7ccf81da1b9911f344310ac9d46f7b870c93fd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/Parsing-arch.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/codegen-aarch64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/parse-cfg.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/CMakeLists.txt
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Rebase and fix code generation
Commit: 340c2df3c4922466bb44afcdbe6ff9213a040fe5
https://github.com/dyninst/dyninst/commit/340c2df3c4922466bb44afcdbe6ff9213a040fe5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V jump instruction generation
Commit: f2cc8cdbe07c458681c432dd4848c479a7aad01e
https://github.com/dyninst/dyninst/commit/f2cc8cdbe07c458681c432dd4848c479a7aad01e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/linux-riscv64-swk.C
Log Message:
-----------
Change gregs to __gregs
Commit: ec310b9eb9c69e5f13fa5d8e58e27cf2a9f471df
https://github.com/dyninst/dyninst/commit/ec310b9eb9c69e5f13fa5d8e58e27cf2a9f471df
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V Long Branch
Commit: 05371d6ff844dd4aee0a5b1650de49a22c2911dd
https://github.com/dyninst/dyninst/commit/05371d6ff844dd4aee0a5b1650de49a22c2911dd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite shifts and constants in RISC-V codegen
Commit: 1ea4067e56e84d03a8da98a2dea8a7acd13c7fd2
https://github.com/dyninst/dyninst/commit/1ea4067e56e84d03a8da98a2dea8a7acd13c7fd2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix wrong indexing order in INSN_SET
Commit: b27bbc0bfaaf07b971dd648b08616c252b91456e
https://github.com/dyninst/dyninst/commit/b27bbc0bfaaf07b971dd648b08616c252b91456e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite load and store using I-Type and S-Type generator
Commit: f3eedeb7143f60c705dc0d09bed5694a0812598f
https://github.com/dyninst/dyninst/commit/f3eedeb7143f60c705dc0d09bed5694a0812598f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Finish emit basic operators
Commit: 390800e92978b1f9bd0b4ab8c99ca9f02135a49b
https://github.com/dyninst/dyninst/commit/390800e92978b1f9bd0b4ab8c99ca9f02135a49b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Add conditional branch
Commit: cd074bbf131db642b45645cfbf2d3797f6005aef
https://github.com/dyninst/dyninst/commit/cd074bbf131db642b45645cfbf2d3797f6005aef
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish emit-riscv64.C
Commit: 10b5c064bd92586f130b478cfa7d056ec3e11ba9
https://github.com/dyninst/dyninst/commit/10b5c064bd92586f130b478cfa7d056ec3e11ba9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
M dataflowAPI/rose/registers/convert.C
M dataflowAPI/rose/registers/riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish inst-riscv64.C
Commit: 7690d1e94fe53ed9b44cd1e2d94321381cc921b4
https://github.com/dyninst/dyninst/commit/7690d1e94fe53ed9b44cd1e2d94321381cc921b4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
Log Message:
-----------
Rewrite RISC-V Branch
Commit: 525ec2fb7fe369be4f5ffd2ed048217475be9812
https://github.com/dyninst/dyninst/commit/525ec2fb7fe369be4f5ffd2ed048217475be9812
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Make dyninstAPI compile
Commit: 9746315287d090a850f14db8c5b78c7f6d17f2d2
https://github.com/dyninst/dyninst/commit/9746315287d090a850f14db8c5b78c7f6d17f2d2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/registers/MachRegister.C
Log Message:
-----------
Update MachRegister
Commit: 8f5420aec2405a763666a6f0dc898b69e4463392
https://github.com/dyninst/dyninst/commit/8f5420aec2405a763666a6f0dc898b69e4463392
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M parseAPI/h/CFGModifier.h
M parseAPI/src/BoundFactCalculator.C
Log Message:
-----------
Fixed missing RISC-V BoundFact
Commit: 5ae01dad327280ea3b63e8d65c25038e749d52bf
https://github.com/dyninst/dyninst/commit/5ae01dad327280ea3b63e8d65c25038e749d52bf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Incorrect plt entry
Commit: 27933f97ee6ec4d23f364b6443615a4153bc764a
https://github.com/dyninst/dyninst/commit/27933f97ee6ec4d23f364b6443615a4153bc764a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
A instructionAPI/src/.gdb_history
M instructionAPI/src/InstructionCategories.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix RISC-V bugs in Instruction API
Commit: 6e29b867b221d087f8e97acf455e1fae19d16648
https://github.com/dyninst/dyninst/commit/6e29b867b221d087f8e97acf455e1fae19d16648
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
M instructionAPI/h/Operation_impl.h
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix some bugs
Commit: 2fc7a6e4054a58a69f5a634e8d357365851c81b8
https://github.com/dyninst/dyninst/commit/2fc7a6e4054a58a69f5a634e8d357365851c81b8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix Segfault in pointer casting
Commit: 423106058411e96547348982adf898945cc9aeaf
https://github.com/dyninst/dyninst/commit/423106058411e96547348982adf898945cc9aeaf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/rose/registers/riscv64.h
Log Message:
-----------
Fix ROSE register conversion I forgot to change after rebase
Commit: cfc0728c32cf926c999baf8732fca7fe5639a854
https://github.com/dyninst/dyninst/commit/cfc0728c32cf926c999baf8732fca7fe5639a854
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add register massaging to jalr
Commit: 3f44bd68ab81ea479455f94a162f8d700c7fb530
https://github.com/dyninst/dyninst/commit/3f44bd68ab81ea479455f94a162f8d700c7fb530
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
M dyninstAPI/src/Relocation/Transformers/Movement-adhoc.C
M dyninstAPI/src/registerSpace.h
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix jr instruction and incorrect fp
Commit: 95438cc249fc0e72daba5805623dd3be6812518f
https://github.com/dyninst/dyninst/commit/95438cc249fc0e72daba5805623dd3be6812518f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Revert wrong readRegister fix
Commit: feb0e0199788be2a3b88da9e95fd63049054b2ee
https://github.com/dyninst/dyninst/commit/feb0e0199788be2a3b88da9e95fd63049054b2ee
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M instructionAPI/src/Instruction.C
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Fix isReturn bug
Commit: e1a36e933cf83dc3d088ce2fa9218a3c3e0e23d8
https://github.com/dyninst/dyninst/commit/e1a36e933cf83dc3d088ce2fa9218a3c3e0e23d8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
Log Message:
-----------
Fixed ud2 in RegisterMap
Commit: bb0ab0ea3b5d98613b37fd8c92cead2b1d64d1bf
https://github.com/dyninst/dyninst/commit/bb0ab0ea3b5d98613b37fd8c92cead2b1d64d1bf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Add riscv attribute
Commit: 06f012a992823f28c7c3f318f03c2ddc897cd09d
https://github.com/dyninst/dyninst/commit/06f012a992823f28c7c3f318f03c2ddc897cd09d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
Log Message:
-----------
Make Dyninst recognize .riscv.attributes
Commit: 96178f5a4d4d550519776babb6d5a356b063588e
https://github.com/dyninst/dyninst/commit/96178f5a4d4d550519776babb6d5a356b063588e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix bug parsing .riscv.attributes
Commit: 123ab0b9c4b336e8644fc6b0ed769ead3a7c637d
https://github.com/dyninst/dyninst/commit/123ab0b9c4b336e8644fc6b0ed769ead3a7c637d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Fix incorrect relocation category
Commit: a1487b299a210c1591a380352e4675db7ff2a7be
https://github.com/dyninst/dyninst/commit/a1487b299a210c1591a380352e4675db7ff2a7be
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Don't know why I missed getRelTypeByElfMachine
Commit: 1db90178d3a9ed6c216ea49810806e3dc14fdb31
https://github.com/dyninst/dyninst/commit/1db90178d3a9ed6c216ea49810806e3dc14fdb31
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
ifdef for libelf compatilibity
Commit: fe91837c383ba18630c7b62a4db7069d984e4f1e
https://github.com/dyninst/dyninst/commit/fe91837c383ba18630c7b62a4db7069d984e4f1e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add library adjust
Commit: c53f01e38b7d1bbbb5cfcf59f7b65e4d5359be25
https://github.com/dyninst/dyninst/commit/c53f01e38b7d1bbbb5cfcf59f7b65e4d5359be25
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add preinit array
Commit: d93cf2810c9b50fb6626e11cd81b42996f5185d2
https://github.com/dyninst/dyninst/commit/d93cf2810c9b50fb6626e11cd81b42996f5185d2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/emitElf.C
Log Message:
-----------
Fix incorrect uleb128 parsing
Commit: 0aa845bc5915a200460968fbed78af413b16c9f2
https://github.com/dyninst/dyninst/commit/0aa845bc5915a200460968fbed78af413b16c9f2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix tag variable shadowing
Commit: 4784e1d29ae1eab7a74930dd64856aa10a7bb6dd
https://github.com/dyninst/dyninst/commit/4784e1d29ae1eab7a74930dd64856aa10a7bb6dd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M symtabAPI/src/emitElf.C
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Null instrumentation now works
Commit: 67fdebd9a5172d282d2bfa84b63d1038931f7f20
https://github.com/dyninst/dyninst/commit/67fdebd9a5172d282d2bfa84b63d1038931f7f20
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Fix incorrect parentheses and generateLoadImm
Commit: db529281c10c13916e8a64e086bd314c91f9d398
https://github.com/dyninst/dyninst/commit/db529281c10c13916e8a64e086bd314c91f9d398
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
is_compressed should be true for C instructions
Commit: adf3fc110aae28dcc818982e59728369a70c9074
https://github.com/dyninst/dyninst/commit/adf3fc110aae28dcc818982e59728369a70c9074
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Fix inconsistency between Capstone and ROSE
Commit: aafe993799974d30e772796be4d61b72422b0f10
https://github.com/dyninst/dyninst/commit/aafe993799974d30e772796be4d61b72422b0f10
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Hardwire x0 to 0
Commit: d880aaf7f53cdc9d62a6722181e2d1cbf267b0fb
https://github.com/dyninst/dyninst/commit/d880aaf7f53cdc9d62a6722181e2d1cbf267b0fb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/codegen-aarch64.C
Log Message:
-----------
Readd disappeared codegen in aarch64
Commit: 0620f90c21d7429efc4398e729df01c6fd262310
https://github.com/dyninst/dyninst/commit/0620f90c21d7429efc4398e729df01c6fd262310
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
emitLoadRelative and emitStoreRelative should be implemented
Commit: e87729ae5034a889c02288d1e44f2f84b8154dbf
https://github.com/dyninst/dyninst/commit/e87729ae5034a889c02288d1e44f2f84b8154dbf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
remove evil constants
Commit: 7636253d0737fdddd717824996dcf9cc86e4f9b0
https://github.com/dyninst/dyninst/commit/7636253d0737fdddd717824996dcf9cc86e4f9b0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
Log Message:
-----------
RISC-V CFWidget
Commit: 5b0e36612e4e0c88a3b0ea9b9f786cddb36aa223
https://github.com/dyninst/dyninst/commit/5b0e36612e4e0c88a3b0ea9b9f786cddb36aa223
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-14 (Wed, 14 May 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
Log Message:
-----------
RISC-V PCWidget
Commit: 9c8e6d08364e9e4eda04cb74d6cde7bcf2c64d8c
https://github.com/dyninst/dyninst/commit/9c8e6d08364e9e4eda04cb74d6cde7bcf2c64d8c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M dyninstAPI/src/parse-cfg.h
M proccontrol/src/riscv_process.C
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix Object ELF
Commit: 72555b7cd87f787bd08a23900f0e6ab019898cfc
https://github.com/dyninst/dyninst/commit/72555b7cd87f787bd08a23900f0e6ab019898cfc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M parseAPI/h/CodeSource.h
M parseAPI/h/InstructionAdapter.h
M parseAPI/src/IA_IAPI.C
M parseAPI/src/IA_IAPI.h
M parseAPI/src/IA_riscv64.C
M parseAPI/src/Parser.C
M parseAPI/src/Parser.h
M parseAPI/src/ParserDetails.C
M parseAPI/src/SymtabCodeSource.C
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Solve RISC-V PLT issue
Compare: https://github.com/dyninst/dyninst/compare/5ed66d82d282...72555b7cd87f
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