Branch: refs/heads/angushe/riscv-codegen
Home: https://github.com/dyninst/dyninst
Commit: 7217540a27f71a0e9162803c4fa4439525dc8506
https://github.com/dyninst/dyninst/commit/7217540a27f71a0e9162803c4fa4439525dc8506
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M CMakeLists.txt
A cmake/tpls/DyninstCapstone.cmake
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Add CMake stub
Commit: 74ca592debfc2d6ba4e91f99d60798f2292bb29b
https://github.com/dyninst/dyninst/commit/74ca592debfc2d6ba4e91f99d60798f2292bb29b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A instructionAPI/capstone/import.py
A instructionAPI/capstone/x86.py
Log Message:
-----------
Make parameter the root directory in import script
Instead of specifying the file name, the user just points to the
directory and the script will grab the necessary files.
Commit: dead3a62fe4540c43a64b1d1ae3c3eacd8e7a166
https://github.com/dyninst/dyninst/commit/dead3a62fe4540c43a64b1d1ae3c3eacd8e7a166
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/capstone/import.py
M instructionAPI/capstone/x86.py
Log Message:
-----------
Alias faddp to fadd
Capstone only uses fadd. This does not modify the entryIDs yet.
Commit: 171c384f7b2aab112c2ebd20b8898d16b491e24f
https://github.com/dyninst/dyninst/commit/171c384f7b2aab112c2ebd20b8898d16b491e24f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/capstone/import.py
Log Message:
-----------
Add mnemonic translation to import script
Commit: e51409e9b80aa800b368824f51651b310fc55c1e
https://github.com/dyninst/dyninst/commit/e51409e9b80aa800b368824f51651b310fc55c1e
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A instructionAPI/src/x86/register-xlat.C
A instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
Add Capstone->Dyninst register translation
Commit: 4766a574b0bc09478b032632fedf4087f89c2bc7
https://github.com/dyninst/dyninst/commit/4766a574b0bc09478b032632fedf4087f89c2bc7
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A instructionAPI/src/x86/mnemonic-xlat.C
A instructionAPI/src/x86/mnemonic-xlat.h
Log Message:
-----------
Add Capstone->Dyninst mnemonic translation
Commit: 31859d2b922f28458f1b5b5466c606f6c79b7b52
https://github.com/dyninst/dyninst/commit/31859d2b922f28458f1b5b5466c606f6c79b7b52
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
A instructionAPI/src/x86/decoder.C
A instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add stub replacement for x86 decoder
Commit: 85a8467c4a440693d3e4fa182253189598f2ada6
https://github.com/dyninst/dyninst/commit/85a8467c4a440693d3e4fa182253189598f2ada6
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add decoder ctor and dtor
There is one usage of Capstone per decoder. This should be threadsafe
as it doesn't make sense to use a decoder with multiple threads
simultaneously. See comments in ctor for why there are two Capstone
handles per decoder.
Commit: 2ca42f2285c32551610427dbc25e5c75b990dafa
https://github.com/dyninst/dyninst/commit/2ca42f2285c32551610427dbc25e5c75b990dafa
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add decodeOpcode
Commit: 140b6a4e1d65ed6c1a179000c3df0df70e1d8b76
https://github.com/dyninst/dyninst/commit/140b6a4e1d65ed6c1a179000c3df0df70e1d8b76
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add note in decodeOperands
Commit: 514c15851b06b08ebef105201ad8071ca7226f21
https://github.com/dyninst/dyninst/commit/514c15851b06b08ebef105201ad8071ca7226f21
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add doDelayedDecode
This is a copy/paste of Xiaozhu's implementation. It appears to be
incomplete (as per the comments).
Commit: 7dfe9b6d10a04646f7d2a1af7eca8e300635731e
https://github.com/dyninst/dyninst/commit/7dfe9b6d10a04646f7d2a1af7eca8e300635731e
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
stub -- refactor
Commit: 9ffa281df5960675a1430acc5cee57eda89ebda1
https://github.com/dyninst/dyninst/commit/9ffa281df5960675a1430acc5cee57eda89ebda1
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Use disassembler object in decode_operands
Commit: b85b4c920af5beba2e882d230b5c775844ef286f
https://github.com/dyninst/dyninst/commit/b85b4c920af5beba2e882d230b5c775844ef286f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Refactor decode_operands
This makes it much easier to follow.
Commit: bbb47620c4beaca7c2afec4d68c5345b2e9ecd81
https://github.com/dyninst/dyninst/commit/bbb47620c4beaca7c2afec4d68c5345b2e9ecd81
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add detailed comments about operand types
Commit: a58a208030d56426fb45a6cf7477ecb85d2cacec
https://github.com/dyninst/dyninst/commit/a58a208030d56426fb45a6cf7477ecb85d2cacec
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use Instruction::makeReturnExpression
No need to reinvent the wheel.
Commit: f163c287ce46d205f0c3085e29c679957cc612cf
https://github.com/dyninst/dyninst/commit/f163c287ce46d205f0c3085e29c679957cc612cf
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove redundant includes
Commit: fd4d1639f2926bf1a715d4dadd58ff589a172cb8
https://github.com/dyninst/dyninst/commit/fd4d1639f2926bf1a715d4dadd58ff589a172cb8
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor handling of implicit registers
By giving the properties names rather than std::pairs, it makes it much
easier to read.
Commit: 543885d651887e7e8f322c6f5e127fb86b85fa04
https://github.com/dyninst/dyninst/commit/543885d651887e7e8f322c6f5e127fb86b85fa04
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Include decoding of {e,r}flags
Commit: ae56d8c42c636ebb59815504bf6f2cd6fd2e127b
https://github.com/dyninst/dyninst/commit/ae56d8c42c636ebb59815504bf6f2cd6fd2e127b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment for explicit operands
Commit: 79a8c4d6a2abc9ee040605349c82c03cd35f82bc
https://github.com/dyninst/dyninst/commit/79a8c4d6a2abc9ee040605349c82c03cd35f82bc
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix explicit operands example
Commit: 902c3dd48fd3d015003c624005252c08f6629bbc
https://github.com/dyninst/dyninst/commit/902c3dd48fd3d015003c624005252c08f6629bbc
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove extraneous namespace qualifier
Commit: 5ea1c1f83a0c3102de21f0e79bc0ca3d9fd225a1
https://github.com/dyninst/dyninst/commit/5ea1c1f83a0c3102de21f0e79bc0ca3d9fd225a1
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor is_call
The original code did the nested check, but didn't need to.
if(cat == c_BranchInsn || cat == c_CallInsn) {
isCFT = true;
if(cat == c_CallInsn) {
isCall = true;
}
}
is equivalent to
if(cat == c_CallInsn) {
isCall = true;
}
if(cat == c_BranchInsn || isCall) {
isCFT = true;
}
Commit: 29597e93f0fe6eac741d52d5b616f082adb53336
https://github.com/dyninst/dyninst/commit/29597e93f0fe6eac741d52d5b616f082adb53336
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment in expand_eflags
Commit: 7f5b4aa1b17699256691c61bc8fd5abe7df2b7d7
https://github.com/dyninst/dyninst/commit/7f5b4aa1b17699256691c61bc8fd5abe7df2b7d7
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/register-xlat.C
Log Message:
-----------
Fix comment for BND registers
Commit: c07f49f5d709bfdc3380d5bcc9cf46edabd3b66c
https://github.com/dyninst/dyninst/commit/c07f49f5d709bfdc3380d5bcc9cf46edabd3b66c
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_reg
Commit: c6a88544aab72a5c04b6077d0118bca1e1f2d58b
https://github.com/dyninst/dyninst/commit/c6a88544aab72a5c04b6077d0118bca1e1f2d58b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_imm
Commit: 5ed418efd696c57b8e67a882fa22aa4e17bd6801
https://github.com/dyninst/dyninst/commit/5ed418efd696c57b8e67a882fa22aa4e17bd6801
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed 64-bit values for immediates
Commit: 92c70f71d287163e315c5a976b58949ed19f7d65
https://github.com/dyninst/dyninst/commit/92c70f71d287163e315c5a976b58949ed19f7d65
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Update comment for relative branch immediates
Commit: 1d51dd67d4b692be82ab310e0c7df375e3b2d9e2
https://github.com/dyninst/dyninst/commit/1d51dd67d4b692be82ab310e0c7df375e3b2d9e2
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove error check on size_to_type
It has been updated to include all values used by Capstone.
Commit: ccb13c0f155026b9014904ac8df82219b6612fb1
https://github.com/dyninst/dyninst/commit/ccb13c0f155026b9014904ac8df82219b6612fb1
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove unneeded assert
Commit: a6fe56569c146b96614b5da5ae48c887edde868b
https://github.com/dyninst/dyninst/commit/a6fe56569c146b96614b5da5ae48c887edde868b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move is_call and is_cft to where they are used
Commit: c1f29963f647344c92026c950863f8b90629b0c1
https://github.com/dyninst/dyninst/commit/c1f29963f647344c92026c950863f8b90629b0c1
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed values for calculations
The manual says everything but the scale can be positive or negative.
Commit: b85c56c2b9860473771c7a7688b39cb8b37616b1
https://github.com/dyninst/dyninst/commit/b85c56c2b9860473771c7a7688b39cb8b37616b1
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use braces
Commit: ee2cd212faa65802206b26daa428c287f9891828
https://github.com/dyninst/dyninst/commit/ee2cd212faa65802206b26daa428c287f9891828
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move size_to_type to where it is used
Commit: e59d875f5cc4fecc7c465309f34b4b39df25e724
https://github.com/dyninst/dyninst/commit/e59d875f5cc4fecc7c465309f34b4b39df25e724
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add some whitespace
Commit: 6bd8701c9c0de01e88e22ce9c2a5e4f1a57d31a6
https://github.com/dyninst/dyninst/commit/6bd8701c9c0de01e88e22ce9c2a5e4f1a57d31a6
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add description from Intel manual
Commit: eeaa4ef19a5f91453219ac0d28898c150200551e
https://github.com/dyninst/dyninst/commit/eeaa4ef19a5f91453219ac0d28898c150200551e
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Return early if processing a CFT
Commit: 52dc159f818bd01c5f9ee67a3ada3456fbe31636
https://github.com/dyninst/dyninst/commit/52dc159f818bd01c5f9ee67a3ada3456fbe31636
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add comment about LEA
Commit: 96ed5fac840bce2e5d90123763251de8f2645537
https://github.com/dyninst/dyninst/commit/96ed5fac840bce2e5d90123763251de8f2645537
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Rename immAST -> displacementAST
This better reflects its meaning.
Commit: 517f5c4fb987dfe44ad018ef2745a2f6113c6740
https://github.com/dyninst/dyninst/commit/517f5c4fb987dfe44ad018ef2745a2f6113c6740
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Handle segment registers as memory operands
Commit: aa354b89a8bc6e10b5167d4a36c7730cc940887f
https://github.com/dyninst/dyninst/commit/aa354b89a8bc6e10b5167d4a36c7730cc940887f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Fix cmake formatting in instructionAPI/CMakeLists.txt
Commit: b38ffc37e5118b08020a474688b8b8392a8cb757
https://github.com/dyninst/dyninst/commit/b38ffc37e5118b08020a474688b8b8392a8cb757
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M .github/workflows/dependency-version.yaml
M docker/dependencies.versions
Log Message:
-----------
Add dependency-version check for Capstone
Commit: 5be386fee060d687b63e84dc8a2253f872330140
https://github.com/dyninst/dyninst/commit/5be386fee060d687b63e84dc8a2253f872330140
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Make Capstone a private dependency
Commit: 1fce2613b5ea552077a9e152b4e83c3d56c9934d
https://github.com/dyninst/dyninst/commit/1fce2613b5ea552077a9e152b4e83c3d56c9934d
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A docker/build_capstone.sh
M docker/dependencies.versions
Log Message:
-----------
Docker: add Capstone builds
Commit: c5f68ced4ae68383727565f87a6746652fcb1da8
https://github.com/dyninst/dyninst/commit/c5f68ced4ae68383727565f87a6746652fcb1da8
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Only decode segment register operands for i386
Commit: f73be44a53aca107158801d6816f0ee72776fd15
https://github.com/dyninst/dyninst/commit/f73be44a53aca107158801d6816f0ee72776fd15
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix format from clang's -Wformat-pedantic
Commit: 101b4c725c124f88a9a20fcef666acb3c967fae1
https://github.com/dyninst/dyninst/commit/101b4c725c124f88a9a20fcef666acb3c967fae1
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M cmake/tpls/DyninstCapstone.cmake
Log Message:
-----------
Use correct capitalization for capstone_ROOT in CMake
Commit: d5fa855d96afc154f83164a3ed7f5303985d9962
https://github.com/dyninst/dyninst/commit/d5fa855d96afc154f83164a3ed7f5303985d9962
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/h/Architecture.h
M dwarf/src/dwarfHandle.C
Log Message:
-----------
Add riscv architecture
Commit: 0d821cc5e5b63c91c143dfb4364a1e17da402375
https://github.com/dyninst/dyninst/commit/0d821cc5e5b63c91c143dfb4364a1e17da402375
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A instructionAPI/capstone/capstone.py
M instructionAPI/capstone/import.py
A instructionAPI/capstone/riscv64.py
Log Message:
-----------
Add riscv64 capstone parser
Commit: b23c8c13b2837006930279940d16c74003e11bc2
https://github.com/dyninst/dyninst/commit/b23c8c13b2837006930279940d16c74003e11bc2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/CMakeLists.txt
M common/h/dyn_regs.h
M common/h/entryIDs.h
A common/h/mnemonics/riscv64_entryIDs.h
A common/h/registers/riscv64_regs.h
A common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add RISC-V registers and mnemonics
Commit: 984ca500f1b9cd805e25df22f3cdbc4fe4a6adc4
https://github.com/dyninst/dyninst/commit/984ca500f1b9cd805e25df22f3cdbc4fe4a6adc4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M elf/src/Elf_X.C
M proccontrol/src/process.C
Log Message:
-----------
Add cases for Arch_riscv64 to suppress compiler warnings
Commit: d708a85db597830f2f6efff4eb62cbd43ba7d89e
https://github.com/dyninst/dyninst/commit/d708a85db597830f2f6efff4eb62cbd43ba7d89e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
M instructionAPI/capstone/import.py
M instructionAPI/h/ArchSpecificFormatters.h
M instructionAPI/src/ArchSpecificFormatters.C
A instructionAPI/src/InstructionDecoder-Capstone.C
A instructionAPI/src/InstructionDecoder-Capstone.h
A instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/InstructionDecoderImpl.C
Log Message:
-----------
Add Capstone-based RISC-V InstructionAPI
Commit: bbf6f8f5d9761623470c6ae692fe40af563d5860
https://github.com/dyninst/dyninst/commit/bbf6f8f5d9761623470c6ae692fe40af563d5860
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M parseAPI/CMakeLists.txt
M parseAPI/src/CodeSource.C
M parseAPI/src/IA_IAPI.C
A parseAPI/src/IA_riscv64.C
A parseAPI/src/IA_riscv64.h
M parseAPI/src/SymbolicExpression.C
Log Message:
-----------
Add RISC-V ParseAPI
Commit: ffebc432f54b0f65cc2990f714c2a8bb4eba23c9
https://github.com/dyninst/dyninst/commit/ffebc432f54b0f65cc2990f714c2a8bb4eba23c9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A dataflowAPI/rose/SgAsmRiscv64Instruction.h
M dataflowAPI/rose/conversions.h
A dataflowAPI/rose/semantics/DispatcherRiscv64.C
A dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/Registers.h
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/RoseImpl.C
M dataflowAPI/src/RoseInsnFactory.C
M dataflowAPI/src/RoseInsnFactory.h
M dataflowAPI/src/SymEval.C
M dataflowAPI/src/SymbolicExpansion.C
M dataflowAPI/src/SymbolicExpansion.h
M dataflowAPI/src/convertOpcodes.C
A external/rose/riscv64InstructionEnum.h
M external/rose/rose-compat.h
Log Message:
-----------
Implement RISC-V DataflowAPI base code
Commit: 042df229376e070bf8c0145e063533ac750f2ceb
https://github.com/dyninst/dyninst/commit/042df229376e070bf8c0145e063533ac750f2ceb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A dataflowAPI/sail/riscv_sail_to_rose.pl
A dataflowAPI/sail/sail_ast.pl
A dataflowAPI/sail/sail_lex.pl
A dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add sail lexical parser
Commit: 105d8008ed32727e12b6382246141e810879ccf7
https://github.com/dyninst/dyninst/commit/105d8008ed32727e12b6382246141e810879ccf7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
rewrite sail lexer using regex
Commit: e47e3eb87350b9d00aa3b33d1c4e49e75210173c
https://github.com/dyninst/dyninst/commit/e47e3eb87350b9d00aa3b33d1c4e49e75210173c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
Use array instead of hash
Commit: e0db05535138ed393fd49f6c7e951f52793c8ba8
https://github.com/dyninst/dyninst/commit/e0db05535138ed393fd49f6c7e951f52793c8ba8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add most syntax
Commit: 326fc21cebb13956f7af4bb9a3b2c91c60173703
https://github.com/dyninst/dyninst/commit/326fc21cebb13956f7af4bb9a3b2c91c60173703
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A dataflowAPI/sail/riscv_ast.json
R dataflowAPI/sail/riscv_sail_to_rose.pl
R dataflowAPI/sail/sail_ast.pl
R dataflowAPI/sail/sail_lex.pl
R dataflowAPI/sail/sail_syntax.pl
A dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (UTYPE)
Commit: 7f8f99f302a17a1bc6e58b6f7ed147819d0fd129
https://github.com/dyninst/dyninst/commit/7f8f99f302a17a1bc6e58b6f7ed147819d0fd129
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/h/Architecture.h
Log Message:
-----------
Add missing riscv64 address width
Commit: 927e49f9dc9d95d9b910ceb578e5ac9b8c129fee
https://github.com/dyninst/dyninst/commit/927e49f9dc9d95d9b910ceb578e5ac9b8c129fee
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (IMAC subsets)
Commit: 8331b7211812b8517d1c3ab0b306638b8ceeca74
https://github.com/dyninst/dyninst/commit/8331b7211812b8517d1c3ab0b306638b8ceeca74
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/src/ExpressionConversionVisitor.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Integrate riscv64 ROSE code into dataflowAPI
Commit: 2e76135244795a3bd27d8fd5c76f33af5286ceed
https://github.com/dyninst/dyninst/commit/2e76135244795a3bd27d8fd5c76f33af5286ceed
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
R instructionAPI/src/x86/decoder.C
R instructionAPI/src/x86/decoder.h
R instructionAPI/src/x86/mnemonic-xlat.C
R instructionAPI/src/x86/mnemonic-xlat.h
R instructionAPI/src/x86/register-xlat.C
R instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
migrate instructionAPI to capstone
Commit: abc503c0b9f121793c6224356d90106875238c6b
https://github.com/dyninst/dyninst/commit/abc503c0b9f121793c6224356d90106875238c6b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/BaseSemantics2.h
A dataflowAPI/rose/semantics/ConcreteSemantics2.C
A dataflowAPI/rose/semantics/ConcreteSemantics2.h
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/SymEvalPolicy.h
Log Message:
-----------
fix mulhsu instruction semantic
Commit: 61648d633489a191074e386b8bc84e6397de3076
https://github.com/dyninst/dyninst/commit/61648d633489a191074e386b8bc84e6397de3076
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M cmake/DyninstPlatform.cmake
M cmake/tpls/DyninstCapstone.cmake
M common/CMakeLists.txt
A common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/src/ABI.C
M dataflowAPI/src/RegisterMap.C
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
A dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget.h
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
A dyninstAPI/src/codegen-riscv64.C
A dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.h
A dyninstAPI/src/emit-riscv64.C
A dyninstAPI/src/emit-riscv64.h
A dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/inst-riscv64.h
A dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/mapped_object.C
A dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI/src/unix.C
M dyninstAPI_RT/CMakeLists.txt
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/CMakeLists.txt
M proccontrol/src/linux.C
M proccontrol/src/linux.h
A proccontrol/src/loadLibrary/codegen-riscv64.C
M proccontrol/src/loadLibrary/codegen.C
M proccontrol/src/loadLibrary/codegen.h
A proccontrol/src/riscv_process.C
A proccontrol/src/riscv_process.h
Log Message:
-----------
Add RISC-V guards
Commit: 75b6d8b485377f91021c7fcf9676da4c16706939
https://github.com/dyninst/dyninst/commit/75b6d8b485377f91021c7fcf9676da4c16706939
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/binaryEdit.C
M dyninstAPI/src/codegen.C
M dyninstAPI/src/function.h
M dyninstAPI/src/linux.C
M stackwalk/CMakeLists.txt
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/framestepper.C
A stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/linux-swk.C
A stackwalk/src/riscv64-swk.C
A stackwalk/src/riscv64-swk.h
M symtabAPI/CMakeLists.txt
M symtabAPI/src/emitElfStatic.C
Log Message:
-----------
Add RISC-V stackwalk guard
Commit: 0f78ef9f4d9c732844fefe2c02c7e520894c6799
https://github.com/dyninst/dyninst/commit/0f78ef9f4d9c732844fefe2c02c7e520894c6799
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A dyninstAPI_RT/src/RTthread-riscv64.c
Log Message:
-----------
Add missing RTthread-riscv64.c
Commit: 465971ada33bb7897c25d4eaefa7bb1fa3d69a64
https://github.com/dyninst/dyninst/commit/465971ada33bb7897c25d4eaefa7bb1fa3d69a64
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A symtabAPI/src/emitElfStatic-riscv64.C
A symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Create RISC-V emitter template
Commit: 6a62e3374a85818d4e96f5261db455ddf173e477
https://github.com/dyninst/dyninst/commit/6a62e3374a85818d4e96f5261db455ddf173e477
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A dyninstAPI_RT/src/RTstatic_ctors_dtors-riscv64.c
Log Message:
-----------
Add missing RTstatic_ctors_dtors-riscv64.c
Commit: ec1dbb73f06e99668a492257709b286cf00a8d10
https://github.com/dyninst/dyninst/commit/ec1dbb73f06e99668a492257709b286cf00a8d10
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dataflowAPI/src/RegisterMap.h
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/RegisterConversion-riscv64.C
A dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
A dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/linux-riscv64.C
A dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.h
A dyninstAPI/src/stackwalk-riscv64.C
M dyninstAPI/src/unix.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
M symtabAPI/src/emitElfStatic-stub.C
Log Message:
-----------
Make RISC-V dyninst compile on a RISC-V machine
Commit: 5a16e94cb0b546bb1fa9a71887d227066f2bdbe1
https://github.com/dyninst/dyninst/commit/5a16e94cb0b546bb1fa9a71887d227066f2bdbe1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
M dyninstAPI/src/linux-riscv64.C
M dyninstAPI/src/parse-riscv64.C
Log Message:
-----------
Implement some instruction emission functions
Commit: 2115cc9c477b1a715440bf0b07a74c02e30152e9
https://github.com/dyninst/dyninst/commit/2115cc9c477b1a715440bf0b07a74c02e30152e9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/registerSpace.h
M external/rose/riscv64InstructionEnum.h
Log Message:
-----------
Amalgamate 32 and 64 bit fpr
Commit: e27885997c1102800a16b447e6dfdbda1751b298
https://github.com/dyninst/dyninst/commit/e27885997c1102800a16b447e6dfdbda1751b298
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Add emitImm
Commit: f2e7df822613756e9a026f0dafc19dd2e6230ecd
https://github.com/dyninst/dyninst/commit/f2e7df822613756e9a026f0dafc19dd2e6230ecd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/src/ABI.C
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/src/linux.C
M stackwalk/src/dbginfo-stepper.C
Log Message:
-----------
Rename arch_riscv64 to DYNINST_HOST_ARCH_AARCH64
Commit: 1a0ce7abff280c41b64b12c83e121ab353df2911
https://github.com/dyninst/dyninst/commit/1a0ce7abff280c41b64b12c83e121ab353df2911
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/CMakeLists.txt
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/convert.C
A dataflowAPI/rose/registers/riscv64.h
M dataflowAPI/src/convertOpcodes.C
M dwarf/CMakeLists.txt
M dwarf/src/registers/convert.C
A dwarf/src/registers/riscv64.h
M dyninstAPI/src/inst-riscv64.h
M external/rose/riscv64InstructionEnum.h
M parseAPI/CMakeLists.txt
Log Message:
-----------
Add missing RISC-V ROSE register conversion
Commit: 35b208e883cda3af9d041838419fec06ba693c2e
https://github.com/dyninst/dyninst/commit/35b208e883cda3af9d041838419fec06ba693c2e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/Instruction.C
Log Message:
-----------
Add missing invalid operand check
Commit: e44dcdafb5993b7d2d344386f1fb87c2f2d07f25
https://github.com/dyninst/dyninst/commit/e44dcdafb5993b7d2d344386f1fb87c2f2d07f25
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/riscv64.h
M dataflowAPI/src/RoseInsnFactory.h
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/mapped_object.C
M instructionAPI/h/Instruction.h
M instructionAPI/src/InstructionDecoder-Capstone.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/interrupts.C
M instructionAPI/src/syscalls.C
M parseAPI/CMakeLists.txt
M parseAPI/src/IA_riscv64.C
M stackwalk/CMakeLists.txt
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
M symtabAPI/CMakeLists.txt
Log Message:
-----------
Modify RISC-V Capstone instruction decoder
Commit: ba6c144d9fe06a9348817451b05683dfb5e95df3
https://github.com/dyninst/dyninst/commit/ba6c144d9fe06a9348817451b05683dfb5e95df3
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Add C-Type Emitter
Commit: ac242746a130993bcaf7903b61bf320bd89de6d4
https://github.com/dyninst/dyninst/commit/ac242746a130993bcaf7903b61bf320bd89de6d4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add Load Immediate
Commit: 54a4314bbff6181d73c27f1307feb25e9188a6a6
https://github.com/dyninst/dyninst/commit/54a4314bbff6181d73c27f1307feb25e9188a6a6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Change insn_size to is_compressed
Commit: 13bf7abc9c5f730348e1e6dc1ab7f376f65ebfa7
https://github.com/dyninst/dyninst/commit/13bf7abc9c5f730348e1e6dc1ab7f376f65ebfa7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add addi codegen
Commit: 6169d3727e9ff159c272afdbf37c5430f56927b9
https://github.com/dyninst/dyninst/commit/6169d3727e9ff159c272afdbf37c5430f56927b9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Optimize addi Code Generation
Commit: 16c4d93b35dc7af77961488cf5427aba6d47870e
https://github.com/dyninst/dyninst/commit/16c4d93b35dc7af77961488cf5427aba6d47870e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M dyninstAPI/CMakeLists.txt
M dyninstAPI_RT/CMakeLists.txt
Log Message:
-----------
Fix DYNINST_ARCH_riscv64
Commit: fb0f86f157ec9f9e1e209640c2fdf5a9853d4c1c
https://github.com/dyninst/dyninst/commit/fb0f86f157ec9f9e1e209640c2fdf5a9853d4c1c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/src/ABI.C
Log Message:
-----------
Add RISC-V initialize64
Commit: 216c9d9bd13ca647d1db6813463f198045c21cc2
https://github.com/dyninst/dyninst/commit/216c9d9bd13ca647d1db6813463f198045c21cc2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/Parsing-arch.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/codegen-aarch64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/parse-cfg.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/CMakeLists.txt
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Rebase and fix code generation
Commit: ddc5101efb7e3d4a2d9fe7fe9ca624cb348c7c8e
https://github.com/dyninst/dyninst/commit/ddc5101efb7e3d4a2d9fe7fe9ca624cb348c7c8e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V jump instruction generation
Commit: 5eb6395fa7c4f3839224844230e8417e6ac4ff6b
https://github.com/dyninst/dyninst/commit/5eb6395fa7c4f3839224844230e8417e6ac4ff6b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/linux-riscv64-swk.C
Log Message:
-----------
Change gregs to __gregs
Commit: d48cfcd2032c3ad3181ff2f42b567da10bb9b452
https://github.com/dyninst/dyninst/commit/d48cfcd2032c3ad3181ff2f42b567da10bb9b452
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V Long Branch
Commit: f51bd7930f3ed32f1920fb63527ef2c336e55b17
https://github.com/dyninst/dyninst/commit/f51bd7930f3ed32f1920fb63527ef2c336e55b17
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite shifts and constants in RISC-V codegen
Commit: 26f1d0ab648610d737a6f4aaf6e170ca54dbc3ce
https://github.com/dyninst/dyninst/commit/26f1d0ab648610d737a6f4aaf6e170ca54dbc3ce
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix wrong indexing order in INSN_SET
Commit: 5f8060593a814bb318ad2add0ccacb2948962979
https://github.com/dyninst/dyninst/commit/5f8060593a814bb318ad2add0ccacb2948962979
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite load and store using I-Type and S-Type generator
Commit: d59f4b004d990cd784e16a8270e1daa44c27cbf6
https://github.com/dyninst/dyninst/commit/d59f4b004d990cd784e16a8270e1daa44c27cbf6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Finish emit basic operators
Commit: fafede98466f08b344f28f7d6dd38a622a93d8b4
https://github.com/dyninst/dyninst/commit/fafede98466f08b344f28f7d6dd38a622a93d8b4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Add conditional branch
Commit: 767022386f5ad4be2574ad33a5472756e22446fc
https://github.com/dyninst/dyninst/commit/767022386f5ad4be2574ad33a5472756e22446fc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish emit-riscv64.C
Commit: a5d0b3b8adb5426c186860a714903967cb20abae
https://github.com/dyninst/dyninst/commit/a5d0b3b8adb5426c186860a714903967cb20abae
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
M dataflowAPI/rose/registers/convert.C
M dataflowAPI/rose/registers/riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish inst-riscv64.C
Commit: c33c57f4438217e27279248fba6a6dddaa4cfaf6
https://github.com/dyninst/dyninst/commit/c33c57f4438217e27279248fba6a6dddaa4cfaf6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
Log Message:
-----------
Rewrite RISC-V Branch
Commit: 3782257151eb052dcfaf638446099e68a3db7bbb
https://github.com/dyninst/dyninst/commit/3782257151eb052dcfaf638446099e68a3db7bbb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Make dyninstAPI compile
Commit: 0d1089df26140031d6fc335308cc840726afe6be
https://github.com/dyninst/dyninst/commit/0d1089df26140031d6fc335308cc840726afe6be
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/registers/MachRegister.C
Log Message:
-----------
Update MachRegister
Commit: c4134ee70a22be4ec35676b59a9fc9a17b09adde
https://github.com/dyninst/dyninst/commit/c4134ee70a22be4ec35676b59a9fc9a17b09adde
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M parseAPI/h/CFGModifier.h
M parseAPI/src/BoundFactCalculator.C
Log Message:
-----------
Fixed missing RISC-V BoundFact
Commit: d5c84a9bb5d87c5b8e94df2f537fee3a61153803
https://github.com/dyninst/dyninst/commit/d5c84a9bb5d87c5b8e94df2f537fee3a61153803
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Incorrect plt entry
Commit: b9d644e54de8e1c74d3bf74c596f8776bb1033b1
https://github.com/dyninst/dyninst/commit/b9d644e54de8e1c74d3bf74c596f8776bb1033b1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
A instructionAPI/src/.gdb_history
M instructionAPI/src/InstructionCategories.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix RISC-V bugs in Instruction API
Commit: f27b336b4bad4fb2ad32128a061afce953f42286
https://github.com/dyninst/dyninst/commit/f27b336b4bad4fb2ad32128a061afce953f42286
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
M instructionAPI/h/Operation_impl.h
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix some bugs
Commit: 5b0c80fd6cb918482a7e1aaeb5b25ba31e77f153
https://github.com/dyninst/dyninst/commit/5b0c80fd6cb918482a7e1aaeb5b25ba31e77f153
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix Segfault in pointer casting
Commit: eab750ae2dd487413387b3ddfd076719047bdb1a
https://github.com/dyninst/dyninst/commit/eab750ae2dd487413387b3ddfd076719047bdb1a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/rose/registers/riscv64.h
Log Message:
-----------
Fix ROSE register conversion I forgot to change after rebase
Commit: 8f69ed09546bb24c155330de19df0deb6e30f6df
https://github.com/dyninst/dyninst/commit/8f69ed09546bb24c155330de19df0deb6e30f6df
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add register massaging to jalr
Commit: 68347d422d095027cf9a2e035dc3464a6d5cd7f7
https://github.com/dyninst/dyninst/commit/68347d422d095027cf9a2e035dc3464a6d5cd7f7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
M dyninstAPI/src/Relocation/Transformers/Movement-adhoc.C
M dyninstAPI/src/registerSpace.h
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix jr instruction and incorrect fp
Commit: 0d3d32f4fbbb3dad14e30387cac1c21e9eadf42f
https://github.com/dyninst/dyninst/commit/0d3d32f4fbbb3dad14e30387cac1c21e9eadf42f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Revert wrong readRegister fix
Commit: a4826ec5515ca133e38be1ccc2aceab7e207c13f
https://github.com/dyninst/dyninst/commit/a4826ec5515ca133e38be1ccc2aceab7e207c13f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M instructionAPI/src/Instruction.C
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Fix isReturn bug
Commit: a3410bf75b1d225d4d581401951fbb05f3b389a7
https://github.com/dyninst/dyninst/commit/a3410bf75b1d225d4d581401951fbb05f3b389a7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
Log Message:
-----------
Fixed ud2 in RegisterMap
Commit: 2ecbfff9a85e18c3e1006bae2b880d875898d145
https://github.com/dyninst/dyninst/commit/2ecbfff9a85e18c3e1006bae2b880d875898d145
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Add riscv attribute
Commit: 10b9c68e2ca07153f85d04d18e7068fe477e45c0
https://github.com/dyninst/dyninst/commit/10b9c68e2ca07153f85d04d18e7068fe477e45c0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
Log Message:
-----------
Make Dyninst recognize .riscv.attributes
Commit: 2e5feb5e7114ff443edf584872f0697d1fc036b4
https://github.com/dyninst/dyninst/commit/2e5feb5e7114ff443edf584872f0697d1fc036b4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix bug parsing .riscv.attributes
Commit: 80f89b075922925eea662e85e87839e6492dddc2
https://github.com/dyninst/dyninst/commit/80f89b075922925eea662e85e87839e6492dddc2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Fix incorrect relocation category
Commit: 99c387f79e5e9e7c6e62b74f2032b881e6e3bc45
https://github.com/dyninst/dyninst/commit/99c387f79e5e9e7c6e62b74f2032b881e6e3bc45
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Don't know why I missed getRelTypeByElfMachine
Commit: 5ffb42014bc6459958f55664435a5877b1c344a2
https://github.com/dyninst/dyninst/commit/5ffb42014bc6459958f55664435a5877b1c344a2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
ifdef for libelf compatilibity
Commit: 7a2f0fdebb70a8f418ff75c80862833bcbabd6a1
https://github.com/dyninst/dyninst/commit/7a2f0fdebb70a8f418ff75c80862833bcbabd6a1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add library adjust
Commit: 97d9f7517f349d68e09ed68dbc0f6053a58d15b4
https://github.com/dyninst/dyninst/commit/97d9f7517f349d68e09ed68dbc0f6053a58d15b4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add preinit array
Commit: 24c52db2993e5713014e794fb2dad47a38a9ba77
https://github.com/dyninst/dyninst/commit/24c52db2993e5713014e794fb2dad47a38a9ba77
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/emitElf.C
Log Message:
-----------
Fix incorrect uleb128 parsing
Commit: d54d17d614fd8d5d018b7142169ac11b9d4b6806
https://github.com/dyninst/dyninst/commit/d54d17d614fd8d5d018b7142169ac11b9d4b6806
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix tag variable shadowing
Commit: c1bab755ac6b3c46dcb6ed0262425104022422f2
https://github.com/dyninst/dyninst/commit/c1bab755ac6b3c46dcb6ed0262425104022422f2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/emitElf.C
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Null instrumentation now works
Commit: 11c55bad898ea287949695e33044cfbdc0628676
https://github.com/dyninst/dyninst/commit/11c55bad898ea287949695e33044cfbdc0628676
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Fix incorrect parentheses and generateLoadImm
Commit: e49d400928f3467ae38801f0638e4aac3c5c638d
https://github.com/dyninst/dyninst/commit/e49d400928f3467ae38801f0638e4aac3c5c638d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
is_compressed should be true for C instructions
Commit: 8e836d80dc0c7d9cf2b4e43c9db87892b75c8fbe
https://github.com/dyninst/dyninst/commit/8e836d80dc0c7d9cf2b4e43c9db87892b75c8fbe
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Fix inconsistency between Capstone and ROSE
Commit: f5dc09c667b6728ed416858f5ddf2988867cd085
https://github.com/dyninst/dyninst/commit/f5dc09c667b6728ed416858f5ddf2988867cd085
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Hardwire x0 to 0
Commit: 390d1c0294237c1bb67feb0f0a4d4e10e2eda325
https://github.com/dyninst/dyninst/commit/390d1c0294237c1bb67feb0f0a4d4e10e2eda325
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/codegen-aarch64.C
Log Message:
-----------
Readd disappeared codegen in aarch64
Commit: de730cb68ef67a4868cbd3e3d9e32f2ef67229b0
https://github.com/dyninst/dyninst/commit/de730cb68ef67a4868cbd3e3d9e32f2ef67229b0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
emitLoadRelative and emitStoreRelative should be implemented
Commit: 3415f97ad9cb41e52061a2126985e6c648ecc55d
https://github.com/dyninst/dyninst/commit/3415f97ad9cb41e52061a2126985e6c648ecc55d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
remove evil constants
Commit: cd7f4f4b6cc928e4cb20431d7150d4fc9188f904
https://github.com/dyninst/dyninst/commit/cd7f4f4b6cc928e4cb20431d7150d4fc9188f904
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
Log Message:
-----------
RISC-V CFWidget
Commit: a7b74a01361563df8a14bb7d90e087f11d8cd4d8
https://github.com/dyninst/dyninst/commit/a7b74a01361563df8a14bb7d90e087f11d8cd4d8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
Log Message:
-----------
RISC-V PCWidget
Commit: a3d84e3fe3708224d53067fd94002ebb51d94733
https://github.com/dyninst/dyninst/commit/a3d84e3fe3708224d53067fd94002ebb51d94733
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
Log Message:
-----------
Add flag to compressed instructions generation
Commit: aacf14d4956f24397c20dfb94d8bc4747a3a6789
https://github.com/dyninst/dyninst/commit/aacf14d4956f24397c20dfb94d8bc4747a3a6789
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/emit-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
A dyninstAPI/src/req.txt
Log Message:
-----------
Huge update
Commit: ce6c74f47f2b573d98b6bc21be74280e7ac18385
https://github.com/dyninst/dyninst/commit/ce6c74f47f2b573d98b6bc21be74280e7ac18385
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-aarch64.h
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Split codegen into multiple of 16 bits
Commit: b45107c39fabdbd84f463eb4b57171041b8203c8
https://github.com/dyninst/dyninst/commit/b45107c39fabdbd84f463eb4b57171041b8203c8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix indexing issue
Commit: 23a7cd099fc62591956e6c40ddfbb512529a0cce
https://github.com/dyninst/dyninst/commit/23a7cd099fc62591956e6c40ddfbb512529a0cce
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix RISC-V ret bugs
Commit: f36eab3e006552df5526da7db4ff4645c42a2b9a
https://github.com/dyninst/dyninst/commit/f36eab3e006552df5526da7db4ff4645c42a2b9a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Fix stack and instruction bugs
Commit: 7172df3aed9ab6739e960029ee23e58ac975bb2f
https://github.com/dyninst/dyninst/commit/7172df3aed9ab6739e960029ee23e58ac975bb2f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Fix long branch bug
Commit: b9ccf5a4a47c918bb7c95a624cfd47c4aed327f7
https://github.com/dyninst/dyninst/commit/b9ccf5a4a47c918bb7c95a624cfd47c4aed327f7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Add modifyData and fix auipc jalr bug
Commit: 0a40493b2ac9398f13cf937079b7d73a3c89bc81
https://github.com/dyninst/dyninst/commit/0a40493b2ac9398f13cf937079b7d73a3c89bc81
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M proccontrol/src/riscv_process.C
Log Message:
-----------
Add Marco's patch
Commit: 17d71d96654dda6aa59bfb0683898af507fbc068
https://github.com/dyninst/dyninst/commit/17d71d96654dda6aa59bfb0683898af507fbc068
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Change PC to read PC register
Commit: 3e36237795b6042e3e9ee1e216ff7b1230995575
https://github.com/dyninst/dyninst/commit/3e36237795b6042e3e9ee1e216ff7b1230995575
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Patch RISC-V SAIL parser
Commit: 9800932ce10d363f01668cdbba0ad05d594559a7
https://github.com/dyninst/dyninst/commit/9800932ce10d363f01668cdbba0ad05d594559a7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
Log Message:
-----------
Fix parse_riscv_attribute API
Commit: f0ee8469cd5525c23a113ee383740a4d3f016f36
https://github.com/dyninst/dyninst/commit/f0ee8469cd5525c23a113ee383740a4d3f016f36
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/linux-riscv64.C
M dyninstAPI/src/parse-riscv64.C
M parseAPI/src/IA_riscv64.C
M proccontrol/src/riscv_process.C
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Fix include arch-riscv64.h
Commit: 7d2b70e608e9fbb2992cf3615320ec4fff107249
https://github.com/dyninst/dyninst/commit/7d2b70e608e9fbb2992cf3615320ec4fff107249
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Revert emitElfStatic-riscv64.C
Commit: 9b85b57917740b4a4e1ee200affe7f4aa7d813fc
https://github.com/dyninst/dyninst/commit/9b85b57917740b4a4e1ee200affe7f4aa7d813fc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M proccontrol/src/riscv_process.C
Log Message:
-----------
Fix Object ELF
Commit: cb922496c64147daf924deb1392617f0631fe5a9
https://github.com/dyninst/dyninst/commit/cb922496c64147daf924deb1392617f0631fe5a9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M parseAPI/h/CodeSource.h
M parseAPI/h/InstructionAdapter.h
M parseAPI/src/IA_IAPI.C
M parseAPI/src/IA_IAPI.h
M parseAPI/src/IA_riscv64.C
M parseAPI/src/Parser.C
M parseAPI/src/Parser.h
M parseAPI/src/ParserDetails.C
M parseAPI/src/SymtabCodeSource.C
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Solve RISC-V PLT issue
Compare: https://github.com/dyninst/dyninst/compare/267635dc2911...cb922496c641
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