Branch: refs/heads/angushe/riscv-support-codegen-arch
Home: https://github.com/dyninst/dyninst
Commit: b74c4cec6e76535c38bf82298fe77a4e29bbda2b
https://github.com/dyninst/dyninst/commit/b74c4cec6e76535c38bf82298fe77a4e29bbda2b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M CMakeLists.txt
A cmake/tpls/DyninstCapstone.cmake
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Add CMake stub
Commit: ace2412a02ae981cf8f2f080809fd7bcd1999322
https://github.com/dyninst/dyninst/commit/ace2412a02ae981cf8f2f080809fd7bcd1999322
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A instructionAPI/capstone/import.py
A instructionAPI/capstone/x86.py
Log Message:
-----------
Make parameter the root directory in import script
Instead of specifying the file name, the user just points to the
directory and the script will grab the necessary files.
Commit: 16bc32db0deb38adf83bde9258e88fec9bab839b
https://github.com/dyninst/dyninst/commit/16bc32db0deb38adf83bde9258e88fec9bab839b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/capstone/import.py
M instructionAPI/capstone/x86.py
Log Message:
-----------
Alias faddp to fadd
Capstone only uses fadd. This does not modify the entryIDs yet.
Commit: 02282e9b2432689557c7d92024e84a7ff483dd39
https://github.com/dyninst/dyninst/commit/02282e9b2432689557c7d92024e84a7ff483dd39
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/capstone/import.py
Log Message:
-----------
Add mnemonic translation to import script
Commit: 106f2e347981bd71d1e5cc47c07d1a1b88780dfc
https://github.com/dyninst/dyninst/commit/106f2e347981bd71d1e5cc47c07d1a1b88780dfc
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A instructionAPI/src/x86/register-xlat.C
A instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
Add Capstone->Dyninst register translation
Commit: 645f4ef39a17745ace0f98d119ac8b0d9e949940
https://github.com/dyninst/dyninst/commit/645f4ef39a17745ace0f98d119ac8b0d9e949940
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A instructionAPI/src/x86/mnemonic-xlat.C
A instructionAPI/src/x86/mnemonic-xlat.h
Log Message:
-----------
Add Capstone->Dyninst mnemonic translation
Commit: 344b84724331ec3830c3a2f1d282e142ddc8321b
https://github.com/dyninst/dyninst/commit/344b84724331ec3830c3a2f1d282e142ddc8321b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
A instructionAPI/src/x86/decoder.C
A instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add stub replacement for x86 decoder
Commit: 247e9a1e1ebf549b6f2a3be508f2b65ac1051930
https://github.com/dyninst/dyninst/commit/247e9a1e1ebf549b6f2a3be508f2b65ac1051930
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add decoder ctor and dtor
There is one usage of Capstone per decoder. This should be threadsafe
as it doesn't make sense to use a decoder with multiple threads
simultaneously. See comments in ctor for why there are two Capstone
handles per decoder.
Commit: f1385dbcc67f5ebb6e7c5391f990e64242e7b791
https://github.com/dyninst/dyninst/commit/f1385dbcc67f5ebb6e7c5391f990e64242e7b791
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add decodeOpcode
Commit: 45fa1b7e63474b3d1319912d43962f25586a561f
https://github.com/dyninst/dyninst/commit/45fa1b7e63474b3d1319912d43962f25586a561f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add note in decodeOperands
Commit: 23f8695436007e6f6c3611eff2ea190eb389f4a7
https://github.com/dyninst/dyninst/commit/23f8695436007e6f6c3611eff2ea190eb389f4a7
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add doDelayedDecode
This is a copy/paste of Xiaozhu's implementation. It appears to be
incomplete (as per the comments).
Commit: 4434bf0d26c7007adafccb113d732ca4fb8d798a
https://github.com/dyninst/dyninst/commit/4434bf0d26c7007adafccb113d732ca4fb8d798a
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
stub -- refactor
Commit: a1731a10ca55ce0d83efc13e4baffb13bfaefcc9
https://github.com/dyninst/dyninst/commit/a1731a10ca55ce0d83efc13e4baffb13bfaefcc9
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Use disassembler object in decode_operands
Commit: a44537bd0a96c1b1129528f8e86efe548b88bde5
https://github.com/dyninst/dyninst/commit/a44537bd0a96c1b1129528f8e86efe548b88bde5
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Refactor decode_operands
This makes it much easier to follow.
Commit: cdb5407a66aaeebc11b995ea67b901ade488b45b
https://github.com/dyninst/dyninst/commit/cdb5407a66aaeebc11b995ea67b901ade488b45b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add detailed comments about operand types
Commit: e2d3fb47b64714b8f395d235eb90b0f926e90f95
https://github.com/dyninst/dyninst/commit/e2d3fb47b64714b8f395d235eb90b0f926e90f95
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use Instruction::makeReturnExpression
No need to reinvent the wheel.
Commit: 9c2a36599727b2212dd1d4e3922fdb2cf1dce5bd
https://github.com/dyninst/dyninst/commit/9c2a36599727b2212dd1d4e3922fdb2cf1dce5bd
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove redundant includes
Commit: 6793b854e354c23254dee421395c2ebd0667e82b
https://github.com/dyninst/dyninst/commit/6793b854e354c23254dee421395c2ebd0667e82b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor handling of implicit registers
By giving the properties names rather than std::pairs, it makes it much
easier to read.
Commit: 0fea54be385d841c39eca667def4314295c4ce85
https://github.com/dyninst/dyninst/commit/0fea54be385d841c39eca667def4314295c4ce85
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Include decoding of {e,r}flags
Commit: 29c74b6dfc24bc312aac5d65106490d008e0a3e3
https://github.com/dyninst/dyninst/commit/29c74b6dfc24bc312aac5d65106490d008e0a3e3
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment for explicit operands
Commit: 9f25abb20189bda7fb2460368ce4ffad3f269fe8
https://github.com/dyninst/dyninst/commit/9f25abb20189bda7fb2460368ce4ffad3f269fe8
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix explicit operands example
Commit: 94451551bc226220032df8c0f4774670d0b3bd43
https://github.com/dyninst/dyninst/commit/94451551bc226220032df8c0f4774670d0b3bd43
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove extraneous namespace qualifier
Commit: 2fc0a4fa230fc57f2e327a6680a467eefcc05a45
https://github.com/dyninst/dyninst/commit/2fc0a4fa230fc57f2e327a6680a467eefcc05a45
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor is_call
The original code did the nested check, but didn't need to.
if(cat == c_BranchInsn || cat == c_CallInsn) {
isCFT = true;
if(cat == c_CallInsn) {
isCall = true;
}
}
is equivalent to
if(cat == c_CallInsn) {
isCall = true;
}
if(cat == c_BranchInsn || isCall) {
isCFT = true;
}
Commit: 868912a597c6a8cfce323c94e478e8835d0fb3f5
https://github.com/dyninst/dyninst/commit/868912a597c6a8cfce323c94e478e8835d0fb3f5
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment in expand_eflags
Commit: fccd0a3adb757ddb7d68ab24bf3e6ff33af36c0b
https://github.com/dyninst/dyninst/commit/fccd0a3adb757ddb7d68ab24bf3e6ff33af36c0b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/register-xlat.C
Log Message:
-----------
Fix comment for BND registers
Commit: 95e3fcba489acc04075d0062989ffb32878a9d0e
https://github.com/dyninst/dyninst/commit/95e3fcba489acc04075d0062989ffb32878a9d0e
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_reg
Commit: 37b814ec48c813bf32da7f83d33a3f0af53faa96
https://github.com/dyninst/dyninst/commit/37b814ec48c813bf32da7f83d33a3f0af53faa96
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_imm
Commit: 74be9b7b8029b1b6ca72798c2d29a1d1b179f05c
https://github.com/dyninst/dyninst/commit/74be9b7b8029b1b6ca72798c2d29a1d1b179f05c
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed 64-bit values for immediates
Commit: 0ebf07aa2a64378a964fcf76458a336f54ec0b14
https://github.com/dyninst/dyninst/commit/0ebf07aa2a64378a964fcf76458a336f54ec0b14
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Update comment for relative branch immediates
Commit: cccbe2ac4f9c56db2f93ecb0567c1b9dfb0d405f
https://github.com/dyninst/dyninst/commit/cccbe2ac4f9c56db2f93ecb0567c1b9dfb0d405f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove error check on size_to_type
It has been updated to include all values used by Capstone.
Commit: d74fb353091091d9d8cbe4f642a5b756ac462f49
https://github.com/dyninst/dyninst/commit/d74fb353091091d9d8cbe4f642a5b756ac462f49
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove unneeded assert
Commit: e2423d3201f36d3254a256fb67cbf574c11fbfe2
https://github.com/dyninst/dyninst/commit/e2423d3201f36d3254a256fb67cbf574c11fbfe2
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move is_call and is_cft to where they are used
Commit: 6a026657d51fcd176174d0c85cbd66106280f6c4
https://github.com/dyninst/dyninst/commit/6a026657d51fcd176174d0c85cbd66106280f6c4
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed values for calculations
The manual says everything but the scale can be positive or negative.
Commit: 5790f1deb4f74d470b0e41fae252ba8ce069e501
https://github.com/dyninst/dyninst/commit/5790f1deb4f74d470b0e41fae252ba8ce069e501
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use braces
Commit: 77f64bba0fa40c6e41309fc9457854ddad02bd74
https://github.com/dyninst/dyninst/commit/77f64bba0fa40c6e41309fc9457854ddad02bd74
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move size_to_type to where it is used
Commit: c93a6dd280746cac0be4cda2efb8690c381737e1
https://github.com/dyninst/dyninst/commit/c93a6dd280746cac0be4cda2efb8690c381737e1
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add some whitespace
Commit: c1edfb3c3051bc70890e48daade8d4e7f19fc5e8
https://github.com/dyninst/dyninst/commit/c1edfb3c3051bc70890e48daade8d4e7f19fc5e8
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add description from Intel manual
Commit: f914bd39d228d62b5246756b8d19ec2a36a85449
https://github.com/dyninst/dyninst/commit/f914bd39d228d62b5246756b8d19ec2a36a85449
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Return early if processing a CFT
Commit: 48a3b4067d7972110b557bbfbb8dd9b34015fdb8
https://github.com/dyninst/dyninst/commit/48a3b4067d7972110b557bbfbb8dd9b34015fdb8
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add comment about LEA
Commit: 65eb38d91a3c80fb3399c8edc092efa47f134ccd
https://github.com/dyninst/dyninst/commit/65eb38d91a3c80fb3399c8edc092efa47f134ccd
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Rename immAST -> displacementAST
This better reflects its meaning.
Commit: 89936b4026b2c7fe17c8d8856a594575e0e2428b
https://github.com/dyninst/dyninst/commit/89936b4026b2c7fe17c8d8856a594575e0e2428b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Handle segment registers as memory operands
Commit: 013a4b80efda87739ae8cfa12ed66437de701de7
https://github.com/dyninst/dyninst/commit/013a4b80efda87739ae8cfa12ed66437de701de7
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Fix cmake formatting in instructionAPI/CMakeLists.txt
Commit: ddbcdade4b3217cfb2958eba5b2f42f106eaa445
https://github.com/dyninst/dyninst/commit/ddbcdade4b3217cfb2958eba5b2f42f106eaa445
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M .github/workflows/dependency-version.yaml
M docker/dependencies.versions
Log Message:
-----------
Add dependency-version check for Capstone
Commit: e2d6291823ffe7b6dffed5085ee948611488624f
https://github.com/dyninst/dyninst/commit/e2d6291823ffe7b6dffed5085ee948611488624f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Make Capstone a private dependency
Commit: a5d214f4f08f11d5d5b0479a88b940b251b766f6
https://github.com/dyninst/dyninst/commit/a5d214f4f08f11d5d5b0479a88b940b251b766f6
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A docker/build_capstone.sh
M docker/dependencies.versions
Log Message:
-----------
Docker: add Capstone builds
Commit: b8e3f8a676846780486fc4248ed674502aeba5eb
https://github.com/dyninst/dyninst/commit/b8e3f8a676846780486fc4248ed674502aeba5eb
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Only decode segment register operands for i386
Commit: f66e8aada2f7ec437547ff3ab1795f7d8d661589
https://github.com/dyninst/dyninst/commit/f66e8aada2f7ec437547ff3ab1795f7d8d661589
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix format from clang's -Wformat-pedantic
Commit: b9721c130e5fa02f4d8965288c0fa29b972a6244
https://github.com/dyninst/dyninst/commit/b9721c130e5fa02f4d8965288c0fa29b972a6244
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M cmake/tpls/DyninstCapstone.cmake
Log Message:
-----------
Use correct capitalization for capstone_ROOT in CMake
Commit: cf1dd85e5057340768517d73e530354054995b4e
https://github.com/dyninst/dyninst/commit/cf1dd85e5057340768517d73e530354054995b4e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/h/Architecture.h
M dwarf/src/dwarfHandle.C
Log Message:
-----------
Add riscv architecture
Commit: 7f0abf0a9418aee23fb350f2da0400285866c171
https://github.com/dyninst/dyninst/commit/7f0abf0a9418aee23fb350f2da0400285866c171
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A instructionAPI/capstone/capstone.py
M instructionAPI/capstone/import.py
A instructionAPI/capstone/riscv64.py
Log Message:
-----------
Add riscv64 capstone parser
Commit: f936db1e9009a6e9fffe0b0a6481ffc14bab7d39
https://github.com/dyninst/dyninst/commit/f936db1e9009a6e9fffe0b0a6481ffc14bab7d39
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/CMakeLists.txt
M common/h/dyn_regs.h
M common/h/entryIDs.h
A common/h/mnemonics/riscv64_entryIDs.h
A common/h/registers/riscv64_regs.h
A common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add RISC-V registers and mnemonics
Commit: d2e5b0e525f197c7396795084fdce3810fc8a11f
https://github.com/dyninst/dyninst/commit/d2e5b0e525f197c7396795084fdce3810fc8a11f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M elf/src/Elf_X.C
M proccontrol/src/process.C
Log Message:
-----------
Add cases for Arch_riscv64 to suppress compiler warnings
Commit: 0d6f13fcd11e771f217b52113428bc3ce8ecddf9
https://github.com/dyninst/dyninst/commit/0d6f13fcd11e771f217b52113428bc3ce8ecddf9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
M instructionAPI/capstone/import.py
M instructionAPI/h/ArchSpecificFormatters.h
M instructionAPI/src/ArchSpecificFormatters.C
A instructionAPI/src/InstructionDecoder-Capstone.C
A instructionAPI/src/InstructionDecoder-Capstone.h
A instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/InstructionDecoderImpl.C
Log Message:
-----------
Add Capstone-based RISC-V InstructionAPI
Commit: 93574c20a3c0d6f768b030e4f86e9c4dfa696a8e
https://github.com/dyninst/dyninst/commit/93574c20a3c0d6f768b030e4f86e9c4dfa696a8e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M parseAPI/CMakeLists.txt
M parseAPI/src/CodeSource.C
M parseAPI/src/IA_IAPI.C
A parseAPI/src/IA_riscv64.C
A parseAPI/src/IA_riscv64.h
M parseAPI/src/SymbolicExpression.C
Log Message:
-----------
Add RISC-V ParseAPI
Commit: 59121e87f8fb39561a62188f4561c25f1d32181c
https://github.com/dyninst/dyninst/commit/59121e87f8fb39561a62188f4561c25f1d32181c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A dataflowAPI/rose/SgAsmRiscv64Instruction.h
M dataflowAPI/rose/conversions.h
A dataflowAPI/rose/semantics/DispatcherRiscv64.C
A dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/Registers.h
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/RoseImpl.C
M dataflowAPI/src/RoseInsnFactory.C
M dataflowAPI/src/RoseInsnFactory.h
M dataflowAPI/src/SymEval.C
M dataflowAPI/src/SymbolicExpansion.C
M dataflowAPI/src/SymbolicExpansion.h
M dataflowAPI/src/convertOpcodes.C
A external/rose/riscv64InstructionEnum.h
M external/rose/rose-compat.h
Log Message:
-----------
Implement RISC-V DataflowAPI base code
Commit: ee52c1274e55fcd92e9b34048adf0d4a16326d57
https://github.com/dyninst/dyninst/commit/ee52c1274e55fcd92e9b34048adf0d4a16326d57
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A dataflowAPI/sail/riscv_sail_to_rose.pl
A dataflowAPI/sail/sail_ast.pl
A dataflowAPI/sail/sail_lex.pl
A dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add sail lexical parser
Commit: 7e2c27d8bb3d329302a40b7cef50aa41da3ebe4e
https://github.com/dyninst/dyninst/commit/7e2c27d8bb3d329302a40b7cef50aa41da3ebe4e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
rewrite sail lexer using regex
Commit: 36024678d22acf43d30e00dbaffbae7b58f9466f
https://github.com/dyninst/dyninst/commit/36024678d22acf43d30e00dbaffbae7b58f9466f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
Use array instead of hash
Commit: 320e7b106c47359334f5b0fa35d5c17ede26a026
https://github.com/dyninst/dyninst/commit/320e7b106c47359334f5b0fa35d5c17ede26a026
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add most syntax
Commit: 4658bba640cccab4ff2098a3b9c6d31389fe73af
https://github.com/dyninst/dyninst/commit/4658bba640cccab4ff2098a3b9c6d31389fe73af
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A dataflowAPI/sail/riscv_ast.json
R dataflowAPI/sail/riscv_sail_to_rose.pl
R dataflowAPI/sail/sail_ast.pl
R dataflowAPI/sail/sail_lex.pl
R dataflowAPI/sail/sail_syntax.pl
A dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (UTYPE)
Commit: 81455d6bd68f916ec86706711243e12ef287fbd9
https://github.com/dyninst/dyninst/commit/81455d6bd68f916ec86706711243e12ef287fbd9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/h/Architecture.h
Log Message:
-----------
Add missing riscv64 address width
Commit: 733c47406246e75f5a465dce773a512033a9b426
https://github.com/dyninst/dyninst/commit/733c47406246e75f5a465dce773a512033a9b426
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (IMAC subsets)
Commit: c404558a4c5f4bcecfc1b2d60196ba1f69797f79
https://github.com/dyninst/dyninst/commit/c404558a4c5f4bcecfc1b2d60196ba1f69797f79
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/src/ExpressionConversionVisitor.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Integrate riscv64 ROSE code into dataflowAPI
Commit: bbeeef2b0887a687647065b01ebd238fe37a902c
https://github.com/dyninst/dyninst/commit/bbeeef2b0887a687647065b01ebd238fe37a902c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
R instructionAPI/src/x86/decoder.C
R instructionAPI/src/x86/decoder.h
R instructionAPI/src/x86/mnemonic-xlat.C
R instructionAPI/src/x86/mnemonic-xlat.h
R instructionAPI/src/x86/register-xlat.C
R instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
migrate instructionAPI to capstone
Commit: efa5349fb0c8a4b1c6d1b3fd1317f40d619df48e
https://github.com/dyninst/dyninst/commit/efa5349fb0c8a4b1c6d1b3fd1317f40d619df48e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/BaseSemantics2.h
A dataflowAPI/rose/semantics/ConcreteSemantics2.C
A dataflowAPI/rose/semantics/ConcreteSemantics2.h
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/SymEvalPolicy.h
Log Message:
-----------
fix mulhsu instruction semantic
Commit: 641e2bc007356d06f170d98dd388b905a9fa8185
https://github.com/dyninst/dyninst/commit/641e2bc007356d06f170d98dd388b905a9fa8185
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M cmake/DyninstPlatform.cmake
M cmake/tpls/DyninstCapstone.cmake
M common/CMakeLists.txt
A common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/src/ABI.C
M dataflowAPI/src/RegisterMap.C
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
A dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget.h
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
A dyninstAPI/src/codegen-riscv64.C
A dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.h
A dyninstAPI/src/emit-riscv64.C
A dyninstAPI/src/emit-riscv64.h
A dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/inst-riscv64.h
A dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/mapped_object.C
A dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI/src/unix.C
M dyninstAPI_RT/CMakeLists.txt
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/CMakeLists.txt
M proccontrol/src/linux.C
M proccontrol/src/linux.h
A proccontrol/src/loadLibrary/codegen-riscv64.C
M proccontrol/src/loadLibrary/codegen.C
M proccontrol/src/loadLibrary/codegen.h
A proccontrol/src/riscv_process.C
A proccontrol/src/riscv_process.h
Log Message:
-----------
Add RISC-V guards
Commit: 7a2b0794926cd7ede0465968babc7985ab6dceac
https://github.com/dyninst/dyninst/commit/7a2b0794926cd7ede0465968babc7985ab6dceac
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/binaryEdit.C
M dyninstAPI/src/codegen.C
M dyninstAPI/src/function.h
M dyninstAPI/src/linux.C
M stackwalk/CMakeLists.txt
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/framestepper.C
A stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/linux-swk.C
A stackwalk/src/riscv64-swk.C
A stackwalk/src/riscv64-swk.h
M symtabAPI/CMakeLists.txt
M symtabAPI/src/emitElfStatic.C
Log Message:
-----------
Add RISC-V stackwalk guard
Commit: e58b9e241dad4c1e56a321de21dc129ecf1001b1
https://github.com/dyninst/dyninst/commit/e58b9e241dad4c1e56a321de21dc129ecf1001b1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A dyninstAPI_RT/src/RTthread-riscv64.c
Log Message:
-----------
Add missing RTthread-riscv64.c
Commit: 14344a7e8002dfb992995617b070e8d36983bd2d
https://github.com/dyninst/dyninst/commit/14344a7e8002dfb992995617b070e8d36983bd2d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A symtabAPI/src/emitElfStatic-riscv64.C
A symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Create RISC-V emitter template
Commit: 79afcd050cfb395b9dfc7a438225a06c38d24231
https://github.com/dyninst/dyninst/commit/79afcd050cfb395b9dfc7a438225a06c38d24231
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A dyninstAPI_RT/src/RTstatic_ctors_dtors-riscv64.c
Log Message:
-----------
Add missing RTstatic_ctors_dtors-riscv64.c
Commit: 6cd49e72a996c6f3c48e079ab4b4e16c0a9b13a4
https://github.com/dyninst/dyninst/commit/6cd49e72a996c6f3c48e079ab4b4e16c0a9b13a4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dataflowAPI/src/RegisterMap.h
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/RegisterConversion-riscv64.C
A dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
A dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/linux-riscv64.C
A dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.h
A dyninstAPI/src/stackwalk-riscv64.C
M dyninstAPI/src/unix.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
M symtabAPI/src/emitElfStatic-stub.C
Log Message:
-----------
Make RISC-V dyninst compile on a RISC-V machine
Commit: ea97f614f383dbcdc5d592d02480d909368ca960
https://github.com/dyninst/dyninst/commit/ea97f614f383dbcdc5d592d02480d909368ca960
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
M dyninstAPI/src/linux-riscv64.C
M dyninstAPI/src/parse-riscv64.C
Log Message:
-----------
Implement some instruction emission functions
Commit: 4c8efeb277114ae5e11332be92f0080f840830ac
https://github.com/dyninst/dyninst/commit/4c8efeb277114ae5e11332be92f0080f840830ac
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/registerSpace.h
M external/rose/riscv64InstructionEnum.h
Log Message:
-----------
Amalgamate 32 and 64 bit fpr
Commit: c96d1f6431f40a1fa8f9a4b7d14b741333b2325a
https://github.com/dyninst/dyninst/commit/c96d1f6431f40a1fa8f9a4b7d14b741333b2325a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Add emitImm
Commit: a871b1c296329a3b5eeccfb825d66212edae9fbe
https://github.com/dyninst/dyninst/commit/a871b1c296329a3b5eeccfb825d66212edae9fbe
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/src/ABI.C
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/src/linux.C
M stackwalk/src/dbginfo-stepper.C
Log Message:
-----------
Rename arch_riscv64 to DYNINST_HOST_ARCH_AARCH64
Commit: 8801788a4e3cf9b35550e103f24191219f59118c
https://github.com/dyninst/dyninst/commit/8801788a4e3cf9b35550e103f24191219f59118c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/CMakeLists.txt
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/convert.C
A dataflowAPI/rose/registers/riscv64.h
M dataflowAPI/src/convertOpcodes.C
M dwarf/CMakeLists.txt
M dwarf/src/registers/convert.C
A dwarf/src/registers/riscv64.h
M dyninstAPI/src/inst-riscv64.h
M external/rose/riscv64InstructionEnum.h
M parseAPI/CMakeLists.txt
Log Message:
-----------
Add missing RISC-V ROSE register conversion
Commit: d758e63573fc38cfb5588823aded0683da2d5ef0
https://github.com/dyninst/dyninst/commit/d758e63573fc38cfb5588823aded0683da2d5ef0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/Instruction.C
Log Message:
-----------
Add missing invalid operand check
Commit: 792fdb72262854c2a5dc6e20eb6a7d2aa008ec2a
https://github.com/dyninst/dyninst/commit/792fdb72262854c2a5dc6e20eb6a7d2aa008ec2a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/riscv64.h
M dataflowAPI/src/RoseInsnFactory.h
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/mapped_object.C
M instructionAPI/h/Instruction.h
M instructionAPI/src/InstructionDecoder-Capstone.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/interrupts.C
M instructionAPI/src/syscalls.C
M parseAPI/CMakeLists.txt
M parseAPI/src/IA_riscv64.C
M stackwalk/CMakeLists.txt
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
M symtabAPI/CMakeLists.txt
Log Message:
-----------
Modify RISC-V Capstone instruction decoder
Commit: 16bc3e4906d8a6bda94d96ce5ad7428e862296e2
https://github.com/dyninst/dyninst/commit/16bc3e4906d8a6bda94d96ce5ad7428e862296e2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Add C-Type Emitter
Commit: 4b80cce80ba8c9768d2080ab596c0d19d7234691
https://github.com/dyninst/dyninst/commit/4b80cce80ba8c9768d2080ab596c0d19d7234691
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add Load Immediate
Commit: ff5d2e6e034cd76e7ecbbc4ecec27cd9a8b6d6eb
https://github.com/dyninst/dyninst/commit/ff5d2e6e034cd76e7ecbbc4ecec27cd9a8b6d6eb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Change insn_size to is_compressed
Commit: fbd82c47b88c89b176e125ff8b2acf67a0415a87
https://github.com/dyninst/dyninst/commit/fbd82c47b88c89b176e125ff8b2acf67a0415a87
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add addi codegen
Commit: 1e2e6619393526dc58fe8bcebfc4b7c878bf4be5
https://github.com/dyninst/dyninst/commit/1e2e6619393526dc58fe8bcebfc4b7c878bf4be5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Optimize addi Code Generation
Commit: 032a34ecefa0e040348f7e380917d669683ff207
https://github.com/dyninst/dyninst/commit/032a34ecefa0e040348f7e380917d669683ff207
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M dyninstAPI/CMakeLists.txt
M dyninstAPI_RT/CMakeLists.txt
Log Message:
-----------
Fix DYNINST_ARCH_riscv64
Commit: ea173e089f56a468521939ed625872f0f5d1f5cc
https://github.com/dyninst/dyninst/commit/ea173e089f56a468521939ed625872f0f5d1f5cc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/src/ABI.C
Log Message:
-----------
Add RISC-V initialize64
Commit: 45c6431def0fbc3cae436904fd4579c84d03e272
https://github.com/dyninst/dyninst/commit/45c6431def0fbc3cae436904fd4579c84d03e272
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/Parsing-arch.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/codegen-aarch64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/parse-cfg.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/CMakeLists.txt
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Rebase and fix code generation
Commit: 1cd588dc2628fd9ebf091ebfe5ab493f9ec30a96
https://github.com/dyninst/dyninst/commit/1cd588dc2628fd9ebf091ebfe5ab493f9ec30a96
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V jump instruction generation
Commit: d08fef3f7282de3fefcd5c879db876f2eb3c845f
https://github.com/dyninst/dyninst/commit/d08fef3f7282de3fefcd5c879db876f2eb3c845f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/linux-riscv64-swk.C
Log Message:
-----------
Change gregs to __gregs
Commit: cdfe28a6b4090d83f7f9ff51e5ca72d1011ddee7
https://github.com/dyninst/dyninst/commit/cdfe28a6b4090d83f7f9ff51e5ca72d1011ddee7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V Long Branch
Commit: d339dc8b9aca9efaa9588076cb1848adad77e013
https://github.com/dyninst/dyninst/commit/d339dc8b9aca9efaa9588076cb1848adad77e013
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite shifts and constants in RISC-V codegen
Commit: 66b819c3aefa66dffdffcab5f1b8fb7f8fd16e9c
https://github.com/dyninst/dyninst/commit/66b819c3aefa66dffdffcab5f1b8fb7f8fd16e9c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix wrong indexing order in INSN_SET
Commit: e0921fdd207f3baa399a4ffe2bde81ec2e73ca1d
https://github.com/dyninst/dyninst/commit/e0921fdd207f3baa399a4ffe2bde81ec2e73ca1d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite load and store using I-Type and S-Type generator
Commit: d4e37a12e0e0b13bdf6b75a06fd137a77f842050
https://github.com/dyninst/dyninst/commit/d4e37a12e0e0b13bdf6b75a06fd137a77f842050
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Finish emit basic operators
Commit: 2d54885f5dbf2315bbe159f3bf95ac4b986f4cf4
https://github.com/dyninst/dyninst/commit/2d54885f5dbf2315bbe159f3bf95ac4b986f4cf4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Add conditional branch
Commit: 8e344f9c81a78cf547b24732e7a3f179243630c0
https://github.com/dyninst/dyninst/commit/8e344f9c81a78cf547b24732e7a3f179243630c0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish emit-riscv64.C
Commit: 4c445b345c6756e50c042879d0200890587dd7c3
https://github.com/dyninst/dyninst/commit/4c445b345c6756e50c042879d0200890587dd7c3
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
M dataflowAPI/rose/registers/convert.C
M dataflowAPI/rose/registers/riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish inst-riscv64.C
Commit: 4870ec8621106fc115a49a7a36b9743b85172207
https://github.com/dyninst/dyninst/commit/4870ec8621106fc115a49a7a36b9743b85172207
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
Log Message:
-----------
Rewrite RISC-V Branch
Commit: 27f0cd965c3eb37265b68728dd1423337ebb1592
https://github.com/dyninst/dyninst/commit/27f0cd965c3eb37265b68728dd1423337ebb1592
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Make dyninstAPI compile
Commit: 52e563b2e63d75a540eb1d9196bc06582129f6a6
https://github.com/dyninst/dyninst/commit/52e563b2e63d75a540eb1d9196bc06582129f6a6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/registers/MachRegister.C
Log Message:
-----------
Update MachRegister
Commit: 7cd764bff94521d331dddab1e98a1adbb46dde2a
https://github.com/dyninst/dyninst/commit/7cd764bff94521d331dddab1e98a1adbb46dde2a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M parseAPI/h/CFGModifier.h
M parseAPI/src/BoundFactCalculator.C
Log Message:
-----------
Fixed missing RISC-V BoundFact
Commit: 4f68a108617b6bbc1784030d69b651c5a970b4d8
https://github.com/dyninst/dyninst/commit/4f68a108617b6bbc1784030d69b651c5a970b4d8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Incorrect plt entry
Commit: a7552c5063dbcd64f44336797da5f9da869f608e
https://github.com/dyninst/dyninst/commit/a7552c5063dbcd64f44336797da5f9da869f608e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A instructionAPI/src/.gdb_history
M instructionAPI/src/InstructionCategories.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix RISC-V bugs in Instruction API
Commit: fcca8663a60c47c11008ab4a5243d85ce0a622b8
https://github.com/dyninst/dyninst/commit/fcca8663a60c47c11008ab4a5243d85ce0a622b8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
M instructionAPI/h/Operation_impl.h
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix some bugs
Commit: 89886d021ae18b26a1aa865018f2e3bc56861ed1
https://github.com/dyninst/dyninst/commit/89886d021ae18b26a1aa865018f2e3bc56861ed1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix Segfault in pointer casting
Commit: fa56382cd9ad5b6a74b3fea8e1ba09c5691c17a1
https://github.com/dyninst/dyninst/commit/fa56382cd9ad5b6a74b3fea8e1ba09c5691c17a1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/rose/registers/riscv64.h
Log Message:
-----------
Fix ROSE register conversion I forgot to change after rebase
Commit: 504d23d987a5aacc913cb50d766a29775e9700f4
https://github.com/dyninst/dyninst/commit/504d23d987a5aacc913cb50d766a29775e9700f4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add register massaging to jalr
Commit: 321472f7784c02e0de9f6a7c5e873f873a7fd0c9
https://github.com/dyninst/dyninst/commit/321472f7784c02e0de9f6a7c5e873f873a7fd0c9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
M dyninstAPI/src/Relocation/Transformers/Movement-adhoc.C
M dyninstAPI/src/registerSpace.h
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix jr instruction and incorrect fp
Commit: e6531cd40b5e44864eb94b4472e0a33b1c1728a7
https://github.com/dyninst/dyninst/commit/e6531cd40b5e44864eb94b4472e0a33b1c1728a7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Revert wrong readRegister fix
Commit: 9592b20d89837b5164feb2f41ef6cf399f9efc81
https://github.com/dyninst/dyninst/commit/9592b20d89837b5164feb2f41ef6cf399f9efc81
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/Instruction.C
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Fix isReturn bug
Commit: e22e9267d5b91ce9b8e513950ff10274f5d75c64
https://github.com/dyninst/dyninst/commit/e22e9267d5b91ce9b8e513950ff10274f5d75c64
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
Log Message:
-----------
Fixed ud2 in RegisterMap
Commit: 4b5c5c6ce1dee06c373d205a7a11c6ec3ffa8825
https://github.com/dyninst/dyninst/commit/4b5c5c6ce1dee06c373d205a7a11c6ec3ffa8825
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Add riscv attribute
Commit: d604fac720bcf82a8ce509535b4d45e9dc35a3f0
https://github.com/dyninst/dyninst/commit/d604fac720bcf82a8ce509535b4d45e9dc35a3f0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
Log Message:
-----------
Make Dyninst recognize .riscv.attributes
Commit: 6c9cb4c8c4f5f036f9697a034e330e84ba44526a
https://github.com/dyninst/dyninst/commit/6c9cb4c8c4f5f036f9697a034e330e84ba44526a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix bug parsing .riscv.attributes
Commit: 0aff3aaacf21f07c0171b6e361e82c3f5eb0b6f7
https://github.com/dyninst/dyninst/commit/0aff3aaacf21f07c0171b6e361e82c3f5eb0b6f7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Fix incorrect relocation category
Commit: 2cb699094aa113806ac677198d320465641604d0
https://github.com/dyninst/dyninst/commit/2cb699094aa113806ac677198d320465641604d0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Don't know why I missed getRelTypeByElfMachine
Commit: 06cc2398871e18aa5b2e36d41b31bc75b5224c69
https://github.com/dyninst/dyninst/commit/06cc2398871e18aa5b2e36d41b31bc75b5224c69
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
ifdef for libelf compatilibity
Commit: c31e5c740c491ba07406332a4bbe0a4257e9b09c
https://github.com/dyninst/dyninst/commit/c31e5c740c491ba07406332a4bbe0a4257e9b09c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add library adjust
Commit: 659da649d44f477692c9ecc5cd0e472087a0260a
https://github.com/dyninst/dyninst/commit/659da649d44f477692c9ecc5cd0e472087a0260a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add preinit array
Commit: 4bd39e36b2cad238ba4e53c129d81712109f811d
https://github.com/dyninst/dyninst/commit/4bd39e36b2cad238ba4e53c129d81712109f811d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/emitElf.C
Log Message:
-----------
Fix incorrect uleb128 parsing
Commit: 505b87e3b1a8868436e7a7d4e2dd95677152ba1a
https://github.com/dyninst/dyninst/commit/505b87e3b1a8868436e7a7d4e2dd95677152ba1a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix tag variable shadowing
Commit: f603c275653e5b97af6216f1712b68fa9dbeeebc
https://github.com/dyninst/dyninst/commit/f603c275653e5b97af6216f1712b68fa9dbeeebc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/emitElf.C
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Null instrumentation now works
Commit: 460f5415044499e2d69a41c3a1e788451df1c338
https://github.com/dyninst/dyninst/commit/460f5415044499e2d69a41c3a1e788451df1c338
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Fix incorrect parentheses and generateLoadImm
Commit: 1c5f8f5224b1c5131a57c18213cd14bbaf867850
https://github.com/dyninst/dyninst/commit/1c5f8f5224b1c5131a57c18213cd14bbaf867850
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
is_compressed should be true for C instructions
Commit: 968a33b9fd5e09c3764ebedf4fa08353349b47b5
https://github.com/dyninst/dyninst/commit/968a33b9fd5e09c3764ebedf4fa08353349b47b5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Fix inconsistency between Capstone and ROSE
Commit: 113c931be9fcd411af57bf71db66b6a05aff8220
https://github.com/dyninst/dyninst/commit/113c931be9fcd411af57bf71db66b6a05aff8220
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Hardwire x0 to 0
Commit: 438856517c91165fbdaeb0511524906bad2e4c0e
https://github.com/dyninst/dyninst/commit/438856517c91165fbdaeb0511524906bad2e4c0e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-aarch64.C
Log Message:
-----------
Readd disappeared codegen in aarch64
Commit: 758fa7c4c658725e59804f834f6f6857500a7037
https://github.com/dyninst/dyninst/commit/758fa7c4c658725e59804f834f6f6857500a7037
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
emitLoadRelative and emitStoreRelative should be implemented
Commit: 3557074638c029e867be1f964b96e6d6e90e2f03
https://github.com/dyninst/dyninst/commit/3557074638c029e867be1f964b96e6d6e90e2f03
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
remove evil constants
Commit: ebfeb22eeaa10176d8ee33d379efb911b5f053cc
https://github.com/dyninst/dyninst/commit/ebfeb22eeaa10176d8ee33d379efb911b5f053cc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
Log Message:
-----------
RISC-V CFWidget
Commit: c746bdff64819268d1c3e57686ae62b1149e629b
https://github.com/dyninst/dyninst/commit/c746bdff64819268d1c3e57686ae62b1149e629b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
Log Message:
-----------
RISC-V PCWidget
Commit: 83dbcc9eee4dc089fafe97604f4046d34db6b371
https://github.com/dyninst/dyninst/commit/83dbcc9eee4dc089fafe97604f4046d34db6b371
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
Log Message:
-----------
Add flag to compressed instructions generation
Commit: c26f341e5f4f9f4fe3313f5b5a2dab1d3253babd
https://github.com/dyninst/dyninst/commit/c26f341e5f4f9f4fe3313f5b5a2dab1d3253babd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/emit-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
A dyninstAPI/src/req.txt
Log Message:
-----------
Huge update
Commit: f269611f15a65b2856a57fbd5fa6f2b6717d5c28
https://github.com/dyninst/dyninst/commit/f269611f15a65b2856a57fbd5fa6f2b6717d5c28
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-aarch64.h
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Split codegen into multiple of 16 bits
Commit: 9b478a3b80e01b0580781f6be095a9583363386c
https://github.com/dyninst/dyninst/commit/9b478a3b80e01b0580781f6be095a9583363386c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix indexing issue
Commit: 14d0e18f5304e3e90a3092c164c89ac799f59481
https://github.com/dyninst/dyninst/commit/14d0e18f5304e3e90a3092c164c89ac799f59481
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix RISC-V ret bugs
Commit: 0578d93f81bbdaf3ac4027ff16e49b2d10192003
https://github.com/dyninst/dyninst/commit/0578d93f81bbdaf3ac4027ff16e49b2d10192003
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Fix stack and instruction bugs
Commit: 3ab2263cbb613a6d41c895350aadd2b9bbdf0896
https://github.com/dyninst/dyninst/commit/3ab2263cbb613a6d41c895350aadd2b9bbdf0896
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Fix long branch bug
Commit: cb17efd2d4a2be196e7ce7c87b9cfb4c9959a9a2
https://github.com/dyninst/dyninst/commit/cb17efd2d4a2be196e7ce7c87b9cfb4c9959a9a2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Add modifyData and fix auipc jalr bug
Commit: 34fa4c13fc12f36c5f2cf1c01e20d7c8ed2db655
https://github.com/dyninst/dyninst/commit/34fa4c13fc12f36c5f2cf1c01e20d7c8ed2db655
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M proccontrol/src/riscv_process.C
Log Message:
-----------
Add Marco's patch
Commit: 8c7d6106bd97ab27f522a7309505e39abe16611c
https://github.com/dyninst/dyninst/commit/8c7d6106bd97ab27f522a7309505e39abe16611c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Change PC to read PC register
Commit: d9e0860920d83c7ab4164aac145f47f184549dc0
https://github.com/dyninst/dyninst/commit/d9e0860920d83c7ab4164aac145f47f184549dc0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Patch RISC-V SAIL parser
Commit: d035b93bc14cdd1449bf14ef1064978e589c53d7
https://github.com/dyninst/dyninst/commit/d035b93bc14cdd1449bf14ef1064978e589c53d7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
Log Message:
-----------
Fix parse_riscv_attribute API
Commit: b68f43a625a18564279bbd998c82641cd130007d
https://github.com/dyninst/dyninst/commit/b68f43a625a18564279bbd998c82641cd130007d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/linux-riscv64.C
M dyninstAPI/src/parse-riscv64.C
M parseAPI/src/IA_riscv64.C
M proccontrol/src/riscv_process.C
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Fix include arch-riscv64.h
Commit: 2b46bc892832b54836b46a0546ef2e47771695e8
https://github.com/dyninst/dyninst/commit/2b46bc892832b54836b46a0546ef2e47771695e8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Revert emitElfStatic-riscv64.C
Commit: ec1e1969d19c9528f3e387bd305bfbbb3795761e
https://github.com/dyninst/dyninst/commit/ec1e1969d19c9528f3e387bd305bfbbb3795761e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M proccontrol/src/riscv_process.C
Log Message:
-----------
Fix Object ELF
Commit: 32eefb646fc0d489b2a6287faa99dd8ece5cbf89
https://github.com/dyninst/dyninst/commit/32eefb646fc0d489b2a6287faa99dd8ece5cbf89
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M parseAPI/h/CodeSource.h
M parseAPI/h/InstructionAdapter.h
M parseAPI/src/IA_IAPI.C
M parseAPI/src/IA_IAPI.h
M parseAPI/src/IA_riscv64.C
M parseAPI/src/Parser.C
M parseAPI/src/Parser.h
M parseAPI/src/ParserDetails.C
M parseAPI/src/SymtabCodeSource.C
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Solve RISC-V PLT issue
Commit: 62bb8ad34ef247ff32240365802d17d3efb5a2a9
https://github.com/dyninst/dyninst/commit/62bb8ad34ef247ff32240365802d17d3efb5a2a9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/sail/sail_to_rose.pl
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
64 ->XLENBITS
Commit: b087d8895371ae8c3568d6c8bfa71c8769bc5c62
https://github.com/dyninst/dyninst/commit/b087d8895371ae8c3568d6c8bfa71c8769bc5c62
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite constant constraints
Commit: 7c27a451b49c2e105708b6ae9378f47e841d22b3
https://github.com/dyninst/dyninst/commit/7c27a451b49c2e105708b6ae9378f47e841d22b3
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Implement missing memory codegen and fix wrong emitImm
Commit: cba7ed7d90c1eac2a6f06b35a9abbb8949c3887e
https://github.com/dyninst/dyninst/commit/cba7ed7d90c1eac2a6f06b35a9abbb8949c3887e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add missing instructions in instructionAPI
Commit: af25e1c20ba0c39fda22058ab2235575435924c2
https://github.com/dyninst/dyninst/commit/af25e1c20ba0c39fda22058ab2235575435924c2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix c.lui
Commit: 8ae8abe29c37851cbb92c028e7f428eff431dcea
https://github.com/dyninst/dyninst/commit/8ae8abe29c37851cbb92c028e7f428eff431dcea
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Correct storing registers in emitCall
Commit: 6e3798b4c8b498f7c3473729438ad43928093e59
https://github.com/dyninst/dyninst/commit/6e3798b4c8b498f7c3473729438ad43928093e59
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add missing atomic instruction in InstructionAPI
Commit: ad78dd809f4328d65b1e076a48226b0d4fc8c036
https://github.com/dyninst/dyninst/commit/ad78dd809f4328d65b1e076a48226b0d4fc8c036
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix inter modular function address
Commit: 36bdb65edc317dccda62bb9053fd1c5d4b8d96d0
https://github.com/dyninst/dyninst/commit/36bdb65edc317dccda62bb9053fd1c5d4b8d96d0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Add branch via trap for RISC-V
Commit: cf721c75826c6d123d90bb1c6e2df787d09cd295
https://github.com/dyninst/dyninst/commit/cf721c75826c6d123d90bb1c6e2df787d09cd295
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Pull register space from address space
Commit: ca62f299453b04ad176c3ee7d57aa22a7501e70a
https://github.com/dyninst/dyninst/commit/ca62f299453b04ad176c3ee7d57aa22a7501e70a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI_RT/src/RTlinux.c
Log Message:
-----------
Fix wrong ElfX_Dyn
Commit: a1499b4ed33c3a5117687a46dcb77a3ec3bdca7e
https://github.com/dyninst/dyninst/commit/a1499b4ed33c3a5117687a46dcb77a3ec3bdca7e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix call instruction codegen bugs
Commit: 31c1500559f32e666141a2a19d8b3a094c4121f0
https://github.com/dyninst/dyninst/commit/31c1500559f32e666141a2a19d8b3a094c4121f0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix lui signedness problem
Commit: b4051d6deaa2f625af1175b143eadeedcc71ee2e
https://github.com/dyninst/dyninst/commit/b4051d6deaa2f625af1175b143eadeedcc71ee2e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/emitElfStatic-riscv64.C
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Minor adjustment in RISCV emitElfStatic
Commit: 11518be17ca70be315ac0f6c227c02115b30b22b
https://github.com/dyninst/dyninst/commit/11518be17ca70be315ac0f6c227c02115b30b22b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Add missing addressWidth
Commit: 35f651b958e1429ac8266cabf7a691f8b74fc33f
https://github.com/dyninst/dyninst/commit/35f651b958e1429ac8266cabf7a691f8b74fc33f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen.C
Log Message:
-----------
Variable length buffer
Commit: e3aaa58a7fd5b05106c4633ed7fa93bfaa2b307b
https://github.com/dyninst/dyninst/commit/e3aaa58a7fd5b05106c4633ed7fa93bfaa2b307b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix incorrect offset in emitCall and emitLoadShared
Commit: 9e751cc7c68826b253d4a8902469bee81341b491
https://github.com/dyninst/dyninst/commit/9e751cc7c68826b253d4a8902469bee81341b491
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
beq to bne
Commit: 0877b7c39e8b99b3eb094b52f663298bc64ef659
https://github.com/dyninst/dyninst/commit/0877b7c39e8b99b3eb094b52f663298bc64ef659
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M instructionAPI/src/InstructionDecoder-Capstone.C
Log Message:
-----------
Fix indentation
Commit: 315b713a896d17abcf62e2e2fe2904a6134f5fe7
https://github.com/dyninst/dyninst/commit/315b713a896d17abcf62e2e2fe2904a6134f5fe7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Improve immediate calculation algorithm
Commit: 2f4098d8ee3972b2211a0063d9ffb3b644795735
https://github.com/dyninst/dyninst/commit/2f4098d8ee3972b2211a0063d9ffb3b644795735
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Remove optimization for relative load store
Commit: 80fa78f1f7fe537361ab9c27408f526cab3d6e9b
https://github.com/dyninst/dyninst/commit/80fa78f1f7fe537361ab9c27408f526cab3d6e9b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix conditional branch offset error
Commit: 6b3fe752b5d33a846e78c8bbb6a36102a65c30a9
https://github.com/dyninst/dyninst/commit/6b3fe752b5d33a846e78c8bbb6a36102a65c30a9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix jump offset
Commit: 515e26958256f67dc41ee433101905ac8e458311
https://github.com/dyninst/dyninst/commit/515e26958256f67dc41ee433101905ac8e458311
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Fix jump target in emitIf
Commit: 6d5248bedf1b6661c71e4183b5e84c53ef314d49
https://github.com/dyninst/dyninst/commit/6d5248bedf1b6661c71e4183b5e84c53ef314d49
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Tail Call
Commit: 0be8256e309fc19bfa9365862f627fbca8047426
https://github.com/dyninst/dyninst/commit/0be8256e309fc19bfa9365862f627fbca8047426
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M dataflowAPI/rose/registers/riscv64.h
Log Message:
-----------
Fix typo
Commit: 393f093f180b29d133aae0646b100408a3386801
https://github.com/dyninst/dyninst/commit/393f093f180b29d133aae0646b100408a3386801
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
A dataflowAPI/sail/experimental/sail_semantics.json
A dataflowAPI/sail/experimental/sail_to_rose.pl
Log Message:
-----------
Add Experimental SAIL parser
Commit: fae6474ab439d797dfe09a59f491cfdb9cbaca77
https://github.com/dyninst/dyninst/commit/fae6474ab439d797dfe09a59f491cfdb9cbaca77
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-14 (Mon, 14 Jul 2025)
Changed paths:
M dataflowAPI/src/ABI.C
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
M dyninstAPI/src/Relocation/Widgets/CFWidget.h
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
M dyninstAPI/src/codegen.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI/src/unix.C
Log Message:
-----------
Support DYNINST_CODEGEN_ARCH_RISCV64
Compare: https://github.com/dyninst/dyninst/compare/b74c4cec6e76%5E...fae6474ab439
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