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Tuesday, February 18, 2025
[DynInst_API:] [dyninst/dyninst] 0663df: GithubCI: use spack-provided dyninst when building...
, Tim Haines
Monday, February 17, 2025
[DynInst_API:] [dyninst/dyninst] 4a891c: Fixed missing RISC-V BoundFact
, wxrdnx
[DynInst_API:] [dyninst/dyninst] 8a8319: Update MachRegister
, wxrdnx
[DynInst_API:] [dyninst/dyninst] 077526: Fix RISC-V base register
, wxrdnx
[DynInst_API:] [dyninst/dyninst] d42a28: Fix RISC_V base register
, wxrdnx
Sunday, February 16, 2025
[DynInst_API:] [dyninst/dyninst] 3b74bd: Add RISC-V base register unit test
, wxrdnx
[DynInst_API:] [dyninst/dyninst] a495ad: Make dyninstAPI compile
, wxrdnx
Saturday, February 15, 2025
[DynInst_API:] [dyninst/dyninst] aa82e1: Rewrite RISC-V Branch
, wxrdnx
[DynInst_API:] [dyninst/dyninst] 7754d5: The size of FPRs should be 8
, wxrdnx
[DynInst_API:] [dyninst/dyninst] bf2b46: Make f<N>_32 and f<N>_64 aliases of f<N>
, wxrdnx
[DynInst_API:] [dyninst/dyninst] e7de0d: Update comments on f<N>_32, f<N>_64, and f<N> FPRs
, wxrdnx
Friday, February 14, 2025
[DynInst_API:] [dyninst/dyninst] e7619c: Add CSR check in isFloatingPoint
, wxrdnx
[DynInst_API:] [dyninst/dyninst] c79d4d: Remove RISC-V check in isZeroFlag
, wxrdnx
[DynInst_API:] [dyninst/dyninst] 4f1041: Add a blank line above Arch_riscv64 case
, wxrdnx
[DynInst_API:] [dyninst/dyninst] 002b29: Use regClass for register type comparison
, wxrdnx
Thursday, February 13, 2025
[DynInst_API:] [dyninst/dyninst] 77f268: Finish inst-riscv64.C
, wxrdnx
Wednesday, February 12, 2025
[DynInst_API:] [dyninst/dyninst]
, Tim Haines
[DynInst_API:] [dyninst/dyninst] 6b0825: Move ARM-specific functions out of MachRegister (#...
, Tim Haines
[DynInst_API:] [dyninst/dyninst] c068b8: Move getArchRegFromAbstractReg into dwarfFrameParser
, Tim Haines
Tuesday, February 11, 2025
[DynInst_API:] [dyninst/dyninst] d535f5: [AMDGPU] Fix build error on clang 15
, Ronak Chauhan
[DynInst_API:] [dyninst/dyninst] 3965c4: [AMDGPU][ELF] Don't use library_adjust
, Ronak Chauhan
Monday, February 10, 2025
[DynInst_API:] [dyninst/dyninst] e7ab33: GithubCI: use spack-provided dyninst when building...
, Tim Haines
[DynInst_API:] [dyninst/dyninst] 5b4414: Finish inst-riscv64.C except for emitR
, wxrdnx
Saturday, February 08, 2025
[DynInst_API:] [dyninst/dyninst] f36c61: Finish emit-riscv64.C
, wxrdnx
Friday, February 07, 2025
[DynInst_API:] [dyninst/dyninst] eeac56: Finish emit-riscv64.C
, wxrdnx
Wednesday, February 05, 2025
[DynInst_API:] [dyninst/dyninst] 3375fc: Update comments
, Tim Haines
Tuesday, February 04, 2025
[DynInst_API:] [dyninst/dyninst] f13154: Add RISC-V instruction mnemonics and registers
, wxrdnx
[DynInst_API:] [dyninst/dyninst] 65bc63: Add conditional branch
, wxrdnx
Monday, February 03, 2025
[DynInst_API:] [dyninst/dyninst] 772f5a: Add CMake stub
, wxrdnx
[DynInst_API:] [dyninst/dyninst]
, Tim Haines
[DynInst_API:] [dyninst/dyninst] 0a8d05: Update base registers for AMDGPU (#1868)
, Tim Haines
[DynInst_API:] [dyninst/dyninst] 1d8883: gfx908
, Tim Haines
[DynInst_API:] [dyninst/dyninst] b37d98: Update comments
, Tim Haines
[DynInst_API:] [dyninst/dyninst]
, Tim Haines
[DynInst_API:] [dyninst/dyninst] 116d98: Add ROSE register tests for aarch64 (#1890)
, Tim Haines
[DynInst_API:] [dyninst/dyninst] 060ce8: Add ROSE register tests for aarch64
, Tim Haines
[DynInst_API:] [dyninst/dyninst]
, Tim Haines
[DynInst_API:] [dyninst/dyninst] a10a2d: Fix rose register conversion for x86/x86_64 (#1853)
, Tim Haines
[DynInst_API:] [dyninst/dyninst]
, Tim Haines
[DynInst_API:] [dyninst/dyninst] a47a22: Move .github/README.md into .github/workflows/READ...
, Tim Haines
[DynInst_API:] [dyninst/dyninst] cfbbc7: Correctly handle IP/PC for x86_64
, Tim Haines
[DynInst_API:] [dyninst/dyninst] 121e8a: Add test skeleton
, Tim Haines
[DynInst_API:] [dyninst/dyninst] 49ca93: Rewrite load and store using I-Type and S-Type gen...
, wxrdnx
Sunday, February 02, 2025
[DynInst_API:] [dyninst/dyninst] 1cbe90: Fix wrong indexing order in INSN_SET
, wxrdnx
[DynInst_API:] [dyninst/dyninst] 661884: Rewrite shifts and constants in RISC-V codegen
, wxrdnx
[DynInst_API:] [dyninst/dyninst] 945f3c: Update flag and segment registers
, Tim Haines
[DynInst_API:] [dyninst/dyninst] cad1af: gfx908
, Tim Haines
[DynInst_API:] [dyninst/dyninst] 0714a3: Add ROSE register tests for aarch64
, Tim Haines
[DynInst_API:] [dyninst/dyninst] a5f377: cmake formatting
, Tim Haines
[DynInst_API:] [dyninst/dyninst] d67c49: Treat ppc64 vector registers as FPRs for ROSE
, Tim Haines
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