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SIGARCH-MSG: July 2003 Digest of SIGARCH Messages
This is the July 2003 Digest of SIGARCH Messages (sigarch-jul03):
* Cache Performance for SPEC CPU2000 Benchmarks, Version 3.0
http://www.cs.wisc.edu/multifacet/misc/spec2000cache-data
Submitted by Jason Cantin <jcantin@ece.wisc.edu>
* HPCA-10 Call for Papers
http://www.ac.uma.es/hpca10/
Submitted by Jose Martinez <martinez@csl.cornell.edu>
* HOT Chips 15 Advance Program
http://www.hotchips.org
Submitted by Alan Smith <smith@eecs.berkeley.edu>
* SimFlex Full System Simulation Tools
http://www.ece.cmu.edu/~simflex
Submitted by Babak Falsafi <babak@cmu.edu>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org
* Archive: http://www.cs.wisc.edu/~lists/archive/sigarch-members/maillist.html
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail listserv@acm.org with message body: unsubscribe SIGARCH-MEMBERS
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Doug Burger Office: 3.432 ACES
Assistant Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-471-9442
University of Texas at Austin Fax: 512-232-1413
Taylor Hall 2.124 E-mail: dburger@cs.utexas.edu
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* Cache Performance for SPEC CPU2000 Benchmarks, Version 3.0
Jason Cantin <jcantin@ece.wisc.edu>
Mark Hill <markhill@cs.wisc.edu>
http://www.cs.wisc.edu/multifacet/misc/spec2000cache-data
We have updated our website on SPEC2000 cache behavior. For the
most part, this was to remove errors caused by not distinguishing
nops and prefetches from normal loads in the Alpha ISA. We have
taken the opportunity to add more data as well.
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* HPCA-10 Call for Papers
Call for Papers
HPCA-10
10th International Symposium on High-Performance Computer Architecture
Madrid, Spain
February 14-18, 2004
http://www.ac.uma.es/hpca10/
The International Symposium on High-Performance Computer Architecture
provides a high quality forum for scientists and engineers to present
their latest research findings in this rapidly changing field. Authors
are invited to submit full papers on all aspects of high-performance
computer architecture.
Topics of interest include, but are not limited to:
+ Processor architectures
+ Cache and memory architectures
+ Parallel computer architectures
+ Impact of VLSI scaling techniques
+ Novel architectures for emerging applications
+ Power-efficient architectures
+ High-availability architectures
+ High-performance I/O architectures
+ Embedded and reconfigurable architectures
+ Real-time architectures
+ Interconnect and network interface architectures
+ Network processor architectures
+ Innovative hardware/software trade-offs
+ Simulation and performance evaluation
+ Benchmarking and measurements
Please check the conference web site for submission information:
http://www.ac.uma.es/hpca10/
The submission should not exceed twelve pages in IEEE double column
format. Papers that exceed the length limit or that cannot be viewed
using Adobe Acrobat Reader (version 3.0 or higher) may not be
reviewed. The official submission deadline is July 14, 2003 at 9pm
Pacific Time USA. An automatic extension of one week will be given
without request. No further extensions will be given. Papers may be
submitted for blind review at the option of the authors. Please
indicate whether the paper is a student paper for best student paper
nominations. Please submit proposals for workshops to the workshops
chair by July 14, 2003.
Important dates:
Paper submission deadline: July 14, 2003
Workshop proposals due: July 14, 2003
Author notification: Oct. 6, 2003
Camera ready copy due: Nov. 3, 2003
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* HOT Chips 15 Advance Program
A Symposium on High-Performance Chips - August 17-19, 2003
Memorial Auditorium, Stanford University, Palo Alto, CA
Sunday, August 17, 2003
8:30-12:00 Morning Tutorial Chair: Tadao Nakamura
Test and Reliability: Challenges for Robust System Design
Subhasish Mitra Intel
High quality and reliability of integrated circuits are keys to the
design of robust systems using these parts. Hence, quality and
reliability are rapidly becoming "features" just like performance,
power-consumption and die size, for both computing and communication
applications. Economic analysis shows that it is infeasible to achieve
the high levels of quality and reliability expected by customers without
designing in these features from very early stages of product
development. Techniques for designing quality and reliability features
will be described and the associated future challenges will be
discussed.
The tutorial will include discussions on the cost of quality,
manufacturing defects and test methodologies, design for testability,
test pattern generation, built-in-self-test, infant mortality of
integrated circuits, impact of noise on test and reliability, soft
errors, design techniques for soft error protection, concurrent error
detection and self-repairing systems. Examples from actual products will
be used to illustrate the applicability of these techniques.
Subhasish Mitra is a Senior Staff Engineer at Intel where he works
Design for Testability, Reliability, Manufacturability and Debug. He is
also a Consulting Assistant Professor in Stanford University's EE
Department. Previously, he was the leader of the DARPA-sponsored ROAR
(Reliability Obtained by Adaptive Reconfiguration) project at Stanford,
and a consultant for Agilent's System Chip Testing project. His research
interests include digital testing, fault-tolerant computing, VLSI design
and computer architecture. His recent awards includea Recognition Award
at Intel for developing a break-through compaction methodology for test
cost reduction, and a Best Panel Award at the VLSI Test Symposium.
12:00-1:30 Lunch
1:30-5:00 Afternoon Tutorial Chair: John Wawrzynek
Past and Future of Cryptographic Engineering
Christof Paar Ruhr-Universitaet Bochum
Security has quickly evolved from a rather obscure niche area to an
important aspect of todayB4s IT applications. The recent trend of
pervasive computing will make it necessary to integrate security
functionality in an extremely broad spectrum of applications, from
traditional computers to household appliances. This application range
will force many engineers (without training in cryptography) to think
about efficient ways of implementing crypto functions, which are the
core tools for providing IT security.
This talk will give an overview of the field of IT security, with a
strong focus on cryptographic engineering. After discussing the general
objectives of IT security, we will introduce the types of practical
crypto schemes , case studies that highlight both symmetric and
asymmetric (public-key) algorithms and the challenges of implementing
them in hardware and software, the architecture of a high performance
public-key engine along with the interaction between implementation and
security requirements, and an introduction to side channel attacks
(perhaps the most important attacks against crypto schemes in the real
world).The presentation will conclude with a discussion of future
research challenges.
Christof Paar has the chair for Communication Security
(www.crypto.rub.de/index_eng.html) at the Horst Gortz Institute for IT
Security at the University of Bochum in Germany. As faculty member at
Worcester Polytechnic Institute, he founded the Cryptography and
Information Security Labs and is co-founder of the CHES (Cryptographic
Hardware and Embedded Systems, www.chesworkshop.org) Workshop series. He
has received an NSF CAREER award for research in cryptography and
reconfigurable hardware. Christof Paar has been teaching cryptography
courses inacademia and industry since 1995.
Monday, August 18, 2003
8:45- 9:00 Welcome, Opening Remarks
General Chair: Siamak Arya
Program Co-Chairs: Pradeep Dubey, Mike Flynn
9:00-10:30 Session 1: Supercomputing, Session Chair: John Sell
* Red Storm: A 10,000 node system with reliable, high bandwidth,
low latency interconnect Bob Alverson Cray
* Quadrics QsNet II : A Network for Supercomputing Applications
Fabrizio Petrini, David Addison, Jon Beecroft, David Hewson,Moray McLaren
Los Alamos
* Sub-lithographic Semiconductor Computing Systems Andre DeHon Caltech
10:30-10:55 Break
10:55-11:45 Keynote: Chair: Mike Flynn
Tadashi Watanabe Vice President, High Performance Computing NEC
*The Whole Earth Simulator: World's Fastest Supercomputer
11:45-12:45 Session 2: Embedded, Session Chair: Howard Sachs
* A Multithreaded RISC/DSP Proc. w/ High Speed Interconnect Erik Norden,Infineon
* Intelligent Energy Managementt: an SoC Design Based on ARM926EJ-S,
David Flynn ARM
12:45- 2:00 Lunch
2:00- 3:30 Session 3: Application Specific Chips, Session Chair: Henry Moreton
* RAMP-IV: A Low-Power /High-Performance 2D/3D Graphics
Accelerator for Mobile Multimedia Applications Ramchan Woo, Sungdae Choi,
Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, and Hoi-Jun Yo, KAIST
* LEHK-3C Display Controller with Image Warping Marco Winzker,
Manfred Stephan, Gerd von Husen, Thomas Roselieb Liesegang GmbH
* ReX: A dNTSC Receiver System on Chip, Slobodan Simovich, Dotcast
3:30- 4:00 Break
4:00- 6:00 Session 4: Wireless
Session Chair: Keith Diefendorff
* The Architecture of the IntelAE PXA800F Cellular Processor
Dilip Krishnaswamy, Intel
* BCM2132: GSM/GPRS Handset Baseband w/ Integrated EDGE & Media Functions
Nelson Sollenberger, Li Fung Chang, Paul Lu, Broadcom
* Broadcom WLAN chipset for 802.11 a/b/g,
Jason A. Trachewsky, Arya Behzad, Reza Rofougaran Broadcom
* A UMTS Baseband Receiver Chip for Infrastructure Applications
Sundararajan Sriram, K. Brown, P. Bertrand, F. Moerman, O. Paviot, C.
Sengupta, V. Sundararajan, and A. Gatherer Texas Instruments
6:00- 7:20 Dinner
7:20- 8:50 Panel: Disasters I Have Been Involved With
Moderator: Nick Tredennick
Panelists: TBA
Tuesday, August 19, 2003
8:50-10:20 Session 5: Switching and Routing, Session Chair: Marc Tremblay
* A Single Chip Shared Mem Switch w/ Twelve 10Gb Ethernet Ports
Takeshi Shimizu, Yukihiro Nakagawa, Sridhar Pathi, Yasushi Umezawa,
Takashi Miyoshi, Takeshi Horie, Akira Hattori, Fujitsu
* Terabit Crossbar Switch Core for Multi-Clock-Domain SoCs
Paddy Thomas, Fulcrum
* Adaptive Packet Processor, Bill Lynch, Procket
10:20-10:50 Break
10:50-12:20 Session 6: Security
Session Chair: Pradeep Dubey
* Multi-Gigabit SSL & TLS Record Layer Protocol Processor and
Multi-Gigabit IPSec Processor, Terry Tham, David Chin, Broadcom
* Continuum Security Processor: Micro-Architecture Overview
Srinivas Mantripragada, NetContinuum
* Nitrox-II81 Inline Security Processor, M. Raghib Hussain, Cavium
12:20- 1:40 Lunch
1:40- 2:30 Keynote: Robert F. Leheny, Director - Microsystems
Technology Office DARPA, Session Chair: Alan Smith
* Perspectives on the Future of Microelectronics for Military
Systems
2:30- 4:00 Session 7: Potpourri, Session Chair: Forrest Baskett
* Ubicom MASI - Wireless Network Processor, David Fotland, Ubicom
* A 10 Gbps Ethernet TCP/IP Processor
Jianping Xu, Nitin Borkar, Vasantha Erraguntla, Yatin Hoskote, Tanay
Karnik, Sriram Vangal, Justin Rattner, Intel
* Janus: A Gigaflop VLIW+RISC SoC Tile, Pier Stanislao Paolucci, Atmel
4:00- 4:20 Break
4:20- 6:20 Session 8: Processors, Session Chair: John Crawford
* An Embedded 600Mhz Synthesized Processor, Howard Sachs, Telairity
* POWER5: IBM's Next Generation POWER Microprocessor, Ron Kalla, IBM
* Ultrasparc Gemini: Dual CPU Processor, Henry Kennedy, Sun
* Two New 130nm Itanium 2 Processors for 2003, Harry Muljono, Stefan Rusu,Intel
6:20- 6:30 Closing Remarks
=============================================================
Visit our Web Pages for Registration and Conference Details
Web registration is preferred! You can register on our secure web
server at
http://www.hotchips.org <http://www.hotchips.org/>
On or before August 5th, you can also register by mailing this form to:
We are sorry that we cannot accept phone registrations.
Confirmation of registration will be sent by e-mail.
Web registration closes on August 5, 2003; Registrations after that date
are on-site only..
Registrations must be made on or before July 17, 2002 for advance rates
to apply.
Refund requests must reach us on or before August 5th, and are subject
to a $50 refund fee.
Students are required to show valid picture ID cards confirming their
student status.
For answers to questions about registration, contact us by email at:
registration@hotchips.org
For other information, contact us by email at:
info@hotchips.org
http://www.hot.org <http://www.hot.org/>
http://www.hotchips.org <http://www.hotchips.org/>
========================================================
Fees: Please CIRCLE Appropriate Fees
Advance (on/before 7/17) Late (after 7/17)
Tutorials Conf. Both Tutorials Conf. Both
Member: $75 $240 $315 $150 $380 $530
Non-Member: $90 $325 $415 $150 $475 $620
Student Member: $ 75 $95 $170 $90 $120 $210
Conference registration includes:
* Conference Attendance
* One copy of presentation notes
* Monday and Tuesday luncheons
* Coffee breaks
* Sunday afternoon wine and cheese reception
* Monday HOT Chips evening dinner and Panel
* Monday and Tuesday Parking
Tutorial registration includes:
* Attendance for both Morning and Afternoon tutorials
* One copy of tutorial notes
* Sunday Luncheon
* Coffee breaks
* Sunday afternoon wine and cheese reception
* Sunday Parking
Federal Tax I.D. Number is 13-1656633 for the
Institute Of Electrical & Electronic Engineers
345 E. 47th Street New York, New York 10017
Provide this information to your accounts payable group.
Special Event: Tour of Computer Museum History Center Collection -
Wednesday, August 20.
The Computer History Museum Center is now open to the public on
Wednesdays. There is no fee, and you can make the trip on your own;
More details will be available in the lobby of Memorial Auditorium
during registration, or Email: machus@aol.com for details.
Register Early on the Web: www.hotchips.org
For housing information, visit our web page: http://www.hotchips.org
<http://www.hotchips.org/>
Location:
HOT Chips and HOT Interconnects will be held in Memorial Auditorium on
the Stanford University campus,
Palo Alto, California approximately 24 miles from San Francisco airport
and 15 miles from San Jose airport.
Directions, Maps:
>From San Francisco: take Highway 101 south. From San Jose:
take Highway 101 north.
Exit 101 at Embarcadero Rd. (west) and drive 3 miles until you enter
Stanford campus on Galvez St.
Keep to the left on Galvez, then turn right at Campus Drive. Parking is
between Galvez and Palm Dr.
Walk along Galvez to the end, then turn right for Memorial Auditorium,
opposite Hoover Tower.
Mass transit information is available at
http://www.transitinfo.org/
Maps of Stanford campus and surroundings are at
http://www.stanford.edu/home/visitors/maps.html
Weather: Mid-August is typically in the 80s (F)/ 30s (C) and sunny
during the day.
Nights are much cooler; a light jacket or sweater is appropriate.
Housing:
Hotel information for the area is available at
http://www.stanford.edu/dept/hds/scs/individuals/hotelmotel.html
The Sheraton, Westin, and Stanford Terrace Inn are the closest hotels to
campus. Reservations well in advance are advised.
On campus housing is available in student residences and can be arranged
by contacting the Stanford Summer Conference Office at (650) 725-1429
or summerhousing@conferences.stanford.edu or
http://fmp-web-2.stanford.edu/indivhousing/ .
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