SIGARCH-MSG: May 2003 Digest of SIGARCH Messages

["Doug Burger" <dburger@cs.utexas.edu>]

This is the May 2003 Digest of SIGARCH Messages (sigarch-may03):

* SIGMETRICS 2003 Call for Participation
  http://www.crhc.uiuc.edu/sigm2003/
  Submitted by Dan Rubenstein <danr@cs.columbia.edu>

* HOT Chips 15 conference
  http://www.hotchips.org/
  Submitted by Allen Baum <abaum@3wisemonkeys.net>

* Call for papers -- Second Workshop on non-silicon computation
  http://www.cs.cmu.edu/~phoenix/nsc2  
  Submitted by Nick Carter <npcarter@crhc.uiuc.edu>

* Computer Architecture Letters Issue
  http://www.comp-arch-letters.org
  Submitted by Kevin Skadron <skadron@cs.virginia.edu>


--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org

* Archive: http://www.cs.wisc.edu/~lists/archive/sigarch-members/maillist.html
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  mail listserv@acm.org with message body: unsubscribe SIGARCH-MEMBERS

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Doug Burger			  Office:	       3.432 ACES
Assistant Professor		  Phone:	     512-471-9795
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Taylor Hall 2.124		  E-mail:   dburger@cs.utexas.edu
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* SIGMETRICS 2003 Call for Participation

                      SIGMETRICS 2003
                   San Diego, California
             http://www.crhc.uiuc.edu/sigm2003/


The 2003 ACM SIGMETRICS Conference on the Measurement and
Modeling of Computer Systems takes place June 10-14, 2003 in
San Diego, California, as part of ACM's Federated Computing
Research Conference (FCRC).

Further information about ACM SIGMETRICS 2003, including
the technical program, tutorials and workshops program,
registration, and accommodations, is available at:

  http://www.crhc.uiuc.edu/sigm2003

Information about FCRC is available at:

  http://www.acm.org/fcrc

Important Dates:
===============

May 7, 2003         End of early Conference/Workshop/Tutorial registration

June 10-11, 2003    Tutorials and Workshops

June 12-14, 2003    Conference

Registration is open NOW.  Please make hotel reservations
as soon as possible.


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 * HOT Chips 15 conference
 Stanford University
 August 17-19, 20032
 http://www.hotchips.org/

	HOT Chips 15 Advance  Program
------------------------------------------
	Sunday, 17 August, 2003
------------------------------------------

Morning Tutorial	Subhasish Mitra	Intel
		Test and Reliability: Challenges for Robust System Design					  
Afternoon Tutorial	Christof Paar	Ruhr-Universitaet Bochum	
		Past and Future of Cryptographic Engineering
		
------------------------------------------
	Monday, 18 August, 2003
------------------------------------------
Session1: Supercomputing
 	* Red Storm:  A 10,000 node system with reliable, 
	  	      high bandwidth, low latency interconnect		Cray
	* Quadrics QsNet II : A Network for Supercomputing Applications	Los Alamos 
	* Sub-lithographic Semiconductor Computing Systems		Caltech
Session2: Keynote:        Tadashi Watanabe					NEC
	* The Whole Earth Simulator: World's Fastest Supercomputer	
Session3: Embedded
	* A Multithreaded RISC/DSP Proc. w/ High Speed Interconnect	Infineon
	* Intelligent Enery Mgmt: an SoC Design based on ARM926EJ-S	ARM
Session4: Application Specific Chips
	* RAMP-IV: A Low-Power /High-Performance 2D/3D Graphics 
		Accelerator for Mobile Multimedia Applications.		KAIST
	* LEHK-3C Display Controller with Image Warping		Liesegang GmbH
	* ReX: A dNTSC Receiver System on Chip				Dotcast
Session5: Wireless
	* The Architecture of the Intel=AE PXA800F Cellular Processor	Intel
	* BCM2132: GSM/GPRS Handset Baseband w/ EDGE & Media Functions	Broadcom
	* Broadcom WLAN chipset for 802.11 a/b/g			Broadcom
	* A 3GPP Baseband Receiver Chip for Infrastructure Applications	TI
Session6: Panel:  	    	Moderator: Nick Tredennick	
	* Disasters I Have Been Involved With	

------------------------------------------
	Sunday, 17 August, 2003
------------------------------------------

Session7: Switching and Routing
	* A Single Chip Shared Mem Switch w/ Twelve 10Gb Ethernet Ports	Fujitsu
	* Terabit Clockless Crossbar Switch in 130 nm			Fulcrum
	* Adaptive Packet Processor					Procket
Session8: Security
	* Multi-Gigabit SSL & TLS Record Layer Protocol Processor and  
	  Multi-Gigabit IPSec Processor					Broadcom
	* Continuum Security Processor: Micro-Architecture Overview	NetContiuum
	* Nitrox-II=81 Inline Security Processor				Cavium
Session9: Keynote:  Robert F. Leheny, Director,Microsystems Tech. Office DAR=
PA
	* Perspectives on the Future of Microelectronics for Military Systems	
Session10: Potpourri
	* Ubicom MASI - Wireless Network Processor			Ubicom
	* A 10 Gbps Ethernet TCP/IP Processor				Intel
	* Janus: A Gigaflop VLIW+RISC SoC Tile				Atmel
Session11: Processors
	* An Embedded 600Mhz Synthesized Processor			Telairity
	* POWER5: IBM's Next Generation POWER Microprocessor		IBM
	* Ultrasparc Gemini: Dual CPU Processor				Sun
	* Two New 130nm Itanium 2 Processors for 2003			Intel

This is a preliminary program; changes may occur.  For the most=
 up-to-the-minute 
details on presentations and schedules,  and for registration information,=
 please 
visit our web site where you can also check out HOT Interconnects 11=
 (another HOT 
Symposium being held following HOTChips 15):
	Web: http://www.hotchips.org		Email: info@hotchips.org

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* CALL FOR PAPERS -- SECOND WORKSHOP ON NON-SILICON COMPUTATION

Paper submissions are solicited for the Second Workshop on Non-Silicon
Computation (NSC-2), to be held in conjunction with the 2003
International Symposium on Computer Architecture
(http://www.cs.nyu.edu/isca03) and the 2003 Federated Computing
Research Conference (http://www.acm.org/sigs/conferences/fcrc/).
NSC-1, the First Workshop on Non-Silicon Computation
(http://www.crhc.uiuc.edu/nsc), was held in February, 2002, in
conjunction with the International Symposium on High-Performance
Computer Architecture, and featured twelve presentations by
researchers in the field.

IMPORTANT DEADLINES:

     * Paper submission: May 12, 2003
     * Author Notification: May 19, 2001
     * Camera-Ready Papers: June 1, 2003
     * Workshop Date: June 8, 2003

WORKSHOP INFORMATION:

This one-day workshop will explore the issues involved in creating
computing systems built from devices other than silicon-based 
transistors. The amazing success of computing over the past thirty years 
is based in large part on advances in the fabrication of CMOS-based 
integrated circuits, and both engineers and consumers have come to 
expect and plan for exponential increases in system performance over 
time. However, a number of physical and economic factors threaten the 
continued scaling of CMOS devices, motivating research into computing 
systems based on other technologies.

A number of alternatives to silicon VLSI have been proposed, including
techniques based on molecular electronics, quantum mechanics, and 
biological processes. This workshop will focus on the architectures, 
compilers, and programming models necessary to exploit novel computing 
technologies that will replace (or co-exist with) CMOS.

SUBMISSION INFORMATION:

Authors should submit an extended abstract no longer than 4 pages for
consideration. One electronic copy of the abstract should be submitted
by email to seth+nsc@cs.cmu.edu by May 12, 2003. Authors of accepted 
abstracts will be asked to submit final papers of no more than 8 pages. 
Notification of acceptance will be given by May 19, 2003 and 
camera-ready papers will be due by June 1, 2003. All accepted papers 
will be presented at the workshop and included in a bound proceedings 
that will be distributed at the workshop. In addition, accepted papers 
will be made available on the workshop home page.

PROGRAM CO-CHAIRS:

Nick Carter (University of Illinois at Urbana-Champaign)
Seth Copen Goldstein (Carnegie Mellon University)

WEB PAGE:

http://www.cs.cmu.edu/~phoenix/nsc2

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Computer Architecture Letters is pleased to announce the publication of
another paper online at our website, <http://www.comp-arch-letters.org>;
the abstract appears below.  The papers will appear in print in our next
paper issue.  The print issues are distributed to the entire IEEE
Computer Society TCCA membership, and e-mail notifications of newly
accepted papers are sent on a regular basis to the TCCA and ACM SIGARCH
memberships.

The objective of Letters is to publish short (4-page), timely articles
of high-quality work.  We are very much aware of the long delays in our
field between submissions of manuscripts and their eventual appearance
in print.  We are doing something about that with this journal.  After
a little more than one year of operation, we have maintained an average
turnaround time from submission to author notification of just one
month, with an acceptance rate of 20%.

We encourage the community to continue submitting papers to Letters. 
Submissions are welcomed on any topic in computer architecture,
especially but not limited to: 
   - Microprocessor and multiprocessor systems 
   - Microarchitecture and ILP processors 
   - Workload characterization 
   - Performance evaluation and simulation techniques 
   - Compiler-hardware and operating system-hardware interactions 
   - Interconnect architectures 
   - Memory and cache systems 
   - Power and thermal issues at the architecture level 
   - I/O architectures and techniques 
   - Independent validation of previously published results 
   - Analysis of unsuccessful techniques 
   - Network and embedded-systems processors 
   - Real-time and high-availability architectures 
   - Reconfigurable systems 
The call for papers and instructions for submission can be found at
<http://www.comp-arch-letters.org>


Abstracts
---------
R. Kumar, K. Farkas, N. P. Jouppi, P. Ranganathan, D. M. Tullsen.
"Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core
Architectures." Volume 2, Apr. 2003.

Abstract:

This paper proposes a single-ISA heterogeneous multi-core architecture
as a mechanism to reduce processor power dissipation. It assumes a
single chip containing a diverse set of cores that target different
performance levels and consume different levels of power.  During an
application's execution, system software dynamically chooses the most
appropriate core to meet specific performance and power requirements. 
It describes an example architecture with five cores of varying
performance and complexity.  Initial results demonstrate a five-fold
reduction in energy at a cost of only 25% performance.