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SIGARCH-MSG: April 2003 Digest of SIGARCH Messages
This is the April 2003 Digest of SIGARCH Messages (sigarch-apr03):
* ISCA 2003 Call for Participation
http://isca03.cs.princeton.edu
Submitted by Allan Gottlieb <gottlieb@nyu.edu>
* SIGARCH travel grants for companion care-provider for ISCA 2003
http://isca03.cs.princeton.edu/grants.htm
Submitted by Sarita Adve <sadve@cs.uiuc.edu>
* SIGARCH student travel grants for ISCA 2003
http://isca03.cs.princeton.edu/grants.htm
Submitted by Sarita Adve <sadve@cs.uiuc.edu>
* 2003 International Conference on Parallel Processing (ICPP-03) Call for Papers
http://www.cis.ohio-state.edu/~icpp2003/
Submitted by Sudhanva Gurumurthi <gurumurt@cse.psu.edu>
* 2003 Workshop on Duplicating, Deconstructing, and Debunking Call for Papers
http://www.ece.wisc.edu/~wddd
Submitted by Bryan Black <bryan.black@intel.com>
* First Value-Prediction Workshop
http://www.csl.cornell.edu/VPW1/
Submitted by Martin Burtscher <burtscher@csl.cornell.edu>
* SNIA Worldwide Repository for I/O Traces, Tools and Analysis
http://www.snia.org/apps/IOTTA_Survey/register.php
Submitted by Arnold Jones <td@snia.org>
* IEEE Computer Special Issue on Power- and Temperature-Aware Computing
http://www.computer.org
Submitted by Kevin Skadron <skadron@cs.virginia.edu>
* Computer Architecture Letters
http://www.comp-arch-letters.org
Submitted by Kevin Skadron <skadron@cs.virginia.edu>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org
* Archive: http://www.cs.wisc.edu/~lists/archive/sigarch-members/maillist.html
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail listserv@acm.org with message body: unsubscribe SIGARCH-MEMBERS
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Doug Burger Office: 3.432 ACES
Assistant Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-471-9442
University of Texas at Austin Fax: 512-232-1413
Taylor Hall 2.124 E-mail: dburger@cs.utexas.edu
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* ISCA 2003 Call for Participation
The thirtieth International Symposium on Computer Architecture (ISCA)
will be held at the Town and Country Hotel in San Diego 9-11 June,
2003. ISCA 2003 is a constitutent conference in the ACM Federated
Computing Research Conference (FCRC).
Information about ISCA, including its tutorial/workshop program can be
found at <http://isca03.cs.princeton.edu>.
Information about FCRC, including registration and hotel information
can be found at <"http:acm.org/sigs/conferences/fcrc>.
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* SIGARCH travel grants for companion care-provider for ISCA 2003
http://isca03.cs.princeton.edu/grants.htm
SIGARCH is providing funds for a limited number of travel grants to attend
ISCA 2003 for a companion care-provider for a SIGARCH member who is:
(1) a person with a physical disability necessitating a companion, or
(2) a parent of an infant less than one year old who cannot travel without
the infant and a care-provider for the infant.
The only costs covered are those incurred solely for the transportation of
the companion. Shared transportation expenses, such as taxis, and
non-transportation costs, such as room and board, are not covered. The
application deadline is 9 May 2003 and recipients will be notified
approximately one week later.
The size of grants may be limited due to budgetary constraints. In
particular, there may be upper bounds on specific items, and we may set
different upper bounds based upon the level of involvement (symposium
speaker, vs. workshop speaker, vs. coauthor for example).
Grants will be paid on submission of original travel receipts and a brief
trip report. Grant application forms are available here. To apply for a
grant, email or snail mail a completed application form to:
Allan Gottlieb <gottlieb@nyu.edu>
NEC Research Institute
4 Independence Way
Princeton NJ 08540
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* SIGARCH student travel grants for ISCA 2003
http://isca03.cs.princeton.edu/grants.htm
SIGARCH is providing funds for a limited number of travel grants for student
members of SIGARCH to attend ISCA 2003. Grants can cover transportation,
symposium registration, and lodging (limited to the night before and the
nights of the symposium itself, not workshops or tutorials). Meals are not
covered. The application deadline is 9 May 2003 and recipients will be
notified approximately one week later.
The size of grants may be limited due to budgetary constraints. In
particular there may be upper bounds on specific items, and we may set
different upper bounds based upon the level of involvement (symposium
speaker, vs. workshop speaker, vs. coauthor for example).
Grants will be paid on submission of original travel receipts and a brief
trip report. Grant application forms are available here. To apply for a
grant, email or snail mail a completed application form to:
Allan Gottlieb <gottlieb@nyu.edu>
NEC Laboratories America
4 Independence Way
Princeton NJ 08540
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* 2003 International Conference on Parallel Processing (ICPP-03) Call
for Papers
http://www.cis.ohio-state.edu/~icpp2003/
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* 2003 Workshop on Duplicating, Deconstructing, and Debunking Call for Papers
*************************************************************
CALL FOR PAPERS: WDDD 2003
*************************************************************
Workshop on Duplicating, Deconstructing, and Debunking
http://www.ece.wisc.edu/~wddd
Held in conjunction with ISCA-30
San Diego, CA
June 8, 2003
-------------------------------------------------------------
IMPORTANT DATES
---------------
Abstracts due: April 25, 2003
Submissions due: May 2, 2003
Acceptance: May 18, 2003
Final version: June 1, 2003
WORKSHOP OVERVIEW
-----------------
WDDD provides the computer architecture and microarchitecture
research community a forum for work that validates or
duplicates earlier results; deconstructs prior findings
by providing greater, in-depth insight into causal relationships
or correlations; or debunks earlier findings by describing
precisely how and why proposed techniques fail where earlier
successes were claimed, or succeed where failure was reported.
Traditionally, computer architecture conferences and
workshops focus almost exclusively on novelty and performance,
neglecting an abundance of interesting work that lacks one or
both of these attributes. A significant part of research--in
fact, the backbone of the scientific method--involves independent
validation of existing work and the exploration of strange ideas
that never pan out. This workshop provides a venue for
disseminating such work in our community. Published validation
experiments strengthen existing work, while thorough comparisons
provide new dimensions and perspectives. Studies that refute
or correct existing work also strengthen the research community,
by ensuring that published material is technically correct and
has sound assumptions. Publishing negative or strange or
unexpected results will allow future researchers to learn the
hard lessons of others, without repeating their effort.
This workshop will set a high scientific standard for such
experiments, and will require insightful analysis to justify
all conclusions. The workshop will favor submissions that
provide meaningful insights and point to underlying root causes
for the failure or success of the technique under investigation.
Acceptable work must thoroughly investigate and clearly communicate
why the proposed technique performs as the results indicate.
Rebuttals may be invited for debunking submissions.
SUBMISSION TOPICS
-----------------
* Independent validation of earlier results with meaningful analysis
* In-depth analysis and sensitivity studies that provide further
insight into earlier findings, or identify key parameters or
assumptions that affect the results
* Studies that refute earlier findings, with clear justification
and explanation
* Negative results for ideas that intuitively make sense and
should work, along with explanations for why they do not
SUBMISSION GUIDELINES
---------------------
* Submit a 200-word abstract plus title and list of authors in
plain text email by April 25, 2003, on the workshop website
www.ece.wisc.edu/~wddd
* Submit a 5000-word double-spaced manuscript by May 2, 2003,
as a PS or PDF file on the workshop website www.ece.wisc.edu/~wddd
Inappropriate submissions, as described in the submitted abstract,
will be rejected outright. Similarly, inflammatory, abusive, or
overtly combative and negative submissions will not be considered.
Accepted papers will be published in the ISCA-30 workshop proceedings.
WORKSHOP ORGANIZERS
-------------------
Bryan Black, Intel Labs, bryan.black@intel.com
Mikko Lipasti, University of Wisconsin, mikko@engr.wisc.edu
PROGRAM COMMITTEE
-----------------
Brad Calder, UCSD
Bob Colwell, R & E Colwell
Alvy Lebeck, Duke
Vijay Pai, Rice
Guri Sohi, Wisconsin
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* First Value-Prediction Workshop
http://www.csl.cornell.edu/VPW1/
to be held in conjunction with the
30th International Symposium on Computer Architecture
San Diego, California
Saturday, June 7, 2003
Theme
The first Value-Prediction Workshop (VPW1) encompasses all hardware and
software speculation mechanisms that require multi-bit predictions as
well as value profiling and other value-based optimization techniques.
Topics include but are not limited to
· value predictors (instruction source operands and/or results)
· confidence estimators
· latency predictors
· pre-execution block predictors
· way predictors for set-associative caches
· line eviction/flush predictors
· dependency predictors
· address predictors (prefetchers)
· branch target predictors
· multi-branch predictors (for trace caches)
· value profiling
· value-based optimizations
Important Dates
Submission: April 25 (5pm EDT)
Notification: May 16
Final paper: May 29
Submission Guidelines
Submissions must use at least 10-point fonts, one-inch margins, and are
not to exceed six US letter size pages (including figures and tables).
Submissions must be in PDF. Please email submissions and questions to
vpw1@csl.cornell.edu.
Organizers
Martin Burtscher (Cornell University)
Amer Diwan (University of Colorado at Boulder)
Program Committee
Brad Calder (University of California, San Diego)
Tom Conte (North Carolina State University)
Rajiv Gupta (The University of Arizona)
Mikko H. Lipasti (University of Wisconsin - Madison)
Avi Mendelson (Intel Corporation)
Yiannakis Sazeides (University of Cyprus)
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* SNIA Worldwide Repository for I/O Traces, Tools and Analysis
Storage Network Industry Association (SNIA)
Worldwide Repository for I/O Traces, Tools and Analysis
I/O trace data is a valuable resource that allows the Storage
Industry to provide solutions that better aligns with actual customer
use. In addition trace data allows Academic researchers the ability
to test their research with real world data. Unfortunately, I/O trace
data availability has been rare, so historically the Storage Industry
has been forced to use archaic trace data (sometimes 20 years old in
the Academic Community) to project customer workload requirements
with new products. In an effort to better serve the marketplace that
is demanding improved storage performance, the SNIA I/O Traces, Tools
and Analysis Technical Work Group is constructing the "World Wide
Repository for I/O Traces, Tools and Analysis" - a valuable resource
that will contain traces, tools, and analysis supporting a current
robust population of trace data.
To ensure this repository will be a relevant and efficient resource
for you, we ask your assistance in completing the following survey
(see URL below). The information you provide will be greatly
appreciated.
http://www.snia.org/apps/IOTTA_Survey/register.php
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* IEEE Computer Special Issue on Power- and Temperature-Aware Computing
Guest Editors:
Mircea R. Stan, ECE Department, University of Virginia
Kevin Skadron, CS Department, University of Virginia
Call for Papers: deadline June 1, 2003
Despite the continuous scaling of processes and supply voltages, and the
increased awareness of low-power issues in the computer design and
design automation communities, power consumption by state-of-the-art ICs
has continually increased in recent years. This apparent paradox results
from the increased density enabled by process scaling and a multilayer
interconnect, coupled with increases in area and especially in clock
frequency driven by an insatiable market for high performance systems.
Temperature is also on the verge of becoming a first-class design
constraint along with the more traditional constraints of cost,
performance, and power. The increasing importance of thermal effects
stems from an exponential increase in on-chip power densities, with
today's processors having power densities greater than a hot plate and
within an order of magnitude of a rocket nozzle. An integrated and
coordinated set of design techniques is required in order to
successfully manage growing power and thermal demands while still
meeting performance, reliability, and cost targets.
Research, characterization, and survery papers are requested for the
December 2003 issue of IEEE Computer. This issue will be devoted to the
subjects of Power-Aware and Temperature-Aware Computing, including
run-time and compile-time techniques at the circuit, architecture, and
system levels for improving battery life, current delivery, and
operating temperature; and integrated concerns of reliability and
quality of service. An integrated and coordinated set of design
techniques is required in order to successfully manage growing power and
thermal demands while still meeting performance, reliability, and cost
targets. Example topics of interest include circuit, architecture, and
system techniques for regulating static and dynamic power; improved
models for power, current-delivery, and thermal aspects;
compiler-hardware and OS-hardware cooperation, methods for optimizing
energy efficiency subject to real-time or quality-of-service
requirements, and active-cooling techniques.
Send inquiries to Guest Editors Mircea R. Stan, University of Virginia
(mircea@virginia.edu) and Kevin Skadron, University of Virginia
(skadron@virginia.edu). Submit pdf documents by June 1 to
computer-ma@computer.org and specify the special issue of Power-Aware
and Temperature-Aware Computing.
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* Computer Architecture Letters
Computer Architecture Letters is pleased to announce the publication of
another paper online at our website, <http://www.comp-arch-letters.org>;
the abstract appears below. The papers will appear in print in our next
paper issue. The print issues are distributed to the entire IEEE
Computer Society TCCA membership, and e-mail notifications of newly
accepted papers are sent on a regular basis to the TCCA and ACM SIGARCH
memberships.
The objective of Letters is to publish short (4-page), timely articles
of high-quality work. We are very much aware of the long delays in our
field between submissions of manuscripts and their eventual appearance
in print. We are doing something about that with this journal. After
a little more than one year of operation, we have maintained an average
turnaround time from submission to author notification of just one
month, with an acceptance rate of 20%.
We encourage the community to continue submitting papers to Letters.
Submissions are welcomed on any topic in computer architecture,
especially but not limited to:
- Microprocessor and multiprocessor systems
- Microarchitecture and ILP processors
- Workload characterization
- Performance evaluation and simulation techniques
- Compiler-hardware and operating system-hardware interactions
- Interconnect architectures
- Memory and cache systems
- Power and thermal issues at the architecture level
- I/O architectures and techniques
- Independent validation of previously published results
- Analysis of unsuccessful techniques
- Network and embedded-systems processors
- Real-time and high-availability architectures
- Reconfigurable systems
The call for papers and instructions for submission can be found at
<http://www.comp-arch-letters.org>
Abstracts
---------
K.-H. Sihn, J. Lee, J.-W. Cho. "A Speculative Coherence Scheme using
Decoupling Synchronization for Multiprocessor Systems." Volume 2, Mar.
2003.
Abstract:
This paper proposes a new speculative coherence
scheme, SCDS, for hardware distributed shared memory systems
to reduce the overhead of coherence action in directory-based
cache-coherence protocol. SCDS has two main features,
predicting accurate timing of speculative coherence with
synchronization information and detecting write pattern
(migratory and non-migratory) for exclusive blocks' speculative
coherence action. In our simulation, SCDS outperforms existing
schemes (DSI and LTP) for well-synchronized applications.
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