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SIGARCH-MSG: July 2001 Digest of SIGARCH Messages
Attached is the SIGARCH mailing list digest for July 2001
(grep sigarch-juln01):
* 2001 International Symposium on Low Power Design
http://www.cse.psu.edu/~islped
* HPCA 8 Call for Proposals for Workshops and Tutorials
http://www.eecg.toronto.edu/hpca8
* MASCOTS 2001 Participation http://www.ececs.uc.edu/mascots/
* PACT'01: Parallel Architectures and Compilation Techniques
http://www.ac.upc.es/pact01
* MEDEA Workshop at PACT: MEmory access DEcoupled Architectures
http://www.dii.unisi.it/medea
* Hot Chips http://www.hotchips.org
* Removing yourself from SIGARCH mailing list
--Mark D. Hill
infodir_SIGARCH@acm.org
SIGARCH Information Director
----------------------------------------------------------------------
Mark D. Hill Office 6373 CSS
Professor & Romnes Fellow Phone 608-262-2196
Computer Sciences Department Asstnt 608-265-3402
University of Wisconsin-Madison FAX 608-262-9777
1210 West Dayton Street E-mail markhill@cs.wisc.edu
Madison, WI 53706-1685 USA http://www.cs.wisc.edu/~markhill
----------------------------------------------------------------------
The Advance Program for the
2001 International Symposium on Low Power Design
August 6 and 7
Huntington Beach, California
is available at http://www.cse.psu.edu/~islped
Cut-off date for advance resgistration is July 27th
Submitted by Mary Jane Irwin <mji@cse.psu.edu>.
----------------------------------------------------------------------
8th International Symposium on High Performance Computer Architecture
HPCA-8 Paper submission deadline is July 13 (+ 1 week).
Additional information is available through:
http://www.eecg.toronto.edu/hpca8
HPCA-8 Call for Workshops and Tutorials
Deadline for proposals: July 13, 2002.
E-mail workshop proposals to Antonio Gonzalez, antonio@ac.upc.es
E-mail tutorials proposals to Gus Uht, uht@ele.uri.edu
*** WORKSHOPS ***
Several workshops are planned to be offered in conjunction with HPCA-8,
immediately before the conference proper. Prospective workshop organizers
should send a detailed proposal to the Workshops Chair (Antonio Gonzalez,
antonio@ac.upc.es) by July 13. Organizers are invited to submit proposals
on all aspects of high-performance computer architecture. Topics of
interest include, but are not limited to:
. Processor architectures
. Cache and memory architectures
. Parallel computer architectures
. Novel architectures for emerging applications
. Architectural support for dynamic optimization
. Power-efficient architectures
. High-performance I/O architectures
. Embedded and reconfigurable architectures
. Real-time architectures
. Application-specific processors
. Interconnection networks and network interfaces
. Simulation and performance evaluation
.Interaction between compilers and computer architecture
Please submit your proposal(s) in PDF format only.
The proposal should contain the following:
1. Workshop title
2. Length of workshop (1 or 2 days)
3. Description of the workshop (about 1 page)
4. Name(s) and affiliation(s) of the organizer(s)
*** TUTORIALS ***
Several tutorials are planned to be offered in conjunction with HPCA-8,
immediately before the conference proper. Prospective tutorial presenters
are requested to send a detailed proposal to the tutorials Chair (Gus
Uht, mailto: uht@ele.uri.edu) by July 13. Please submit your proposal(s)
in PDF format only.
The proposal should contain the following:
1. Tutorial Title
2. Length of tutorial (1/2 day or 1 day)
3. Syllabus (brief description of subject matter)
4. Detailed outline (about 1-2 pages single-spaced)
5. Intended audience, including assumed attendee background
6. Name(s), affiliation(s) and resume(s) or CV's of the speaker(s)
7. Special presentation requirements, e.g., data projector.
8. Proposed set of handouts for the attendees.
Submitted by Andreas Moshovos <moshovos@eecg.toronto.edu>
----------------------------------------------------------------------
Call for Participation
M A S C O T S 2001
Ninth International Symposium on Modeling, Analysis and Simulation
of Computer and Telecommunication Systems
August 15-18, 2001, Cincinnati, Ohio, USA
Sponsored by IEEE Computer Society
In Cooperation with ACM SIGSIM and SIGARCH
The advance program and registration details for MASCOTS 2001 are
available via the conference web site:
--------------------------------
http://www.ececs.uc.edu/mascots/
--------------------------------
Symposium Highlights:
--------------------
Tutorials on state-of-the-art topics:
o Teletraffic Models and Tools: From Basics to Advanced
by K. Sohraby (Univ. of Missouri-Kansas City)
o Java Performance
by V. Mainkar (AT&T)
o Network-Based Computing: Issues, Trends and Challenges,
by D. Panda (Ohio State Univ.)
Keynote speeches by leaders of the field:
o Mark Squillante (IBM TJ Watson)
o John Hines (Air Force Research Lab, WPAFB)
o Richard Fujimoto (Georgia Tech)
Paper sessions on timely topics:
o Real-time systems
o Capacity planning
o Broadband
o Wireless systems
o Routing
o Network traffic
o Switching
o File systems
o WWW
o Modeling
o Network simulation/emulation
o Parallel and distributed simulation
o Tools
o Benchmarking
Important Dates:
---------------
13 July, 2001 Advance registration deadline
24 July, 2001 Hotel reservation deadline
15 August, 2001 Tutorial sessions
16-18 August, 2001 Paper sessions
Organizing Committee:
--------------------
o General Chair:
Dharma P. Agarwal (University of Cincinnati)
o Program Chair:
David Nicol (Dartmouth College)
o Program Vice-Chair
Felipe Perrone (Institute for Security Technology
Studies, Dartmouth College)
o Tools Chair:
Azzedine Boukerche (University of North Texas)
o Tutorials Chair:
Philip A. Wilsey (University of Cincinnati)
o Publicity Chair:
Samir R. Das (University of Cincinnati)
o Local Arrangements Chair:
Yiming Hu (University of Cincinnati)
o Registration and Finance Chair:
Karen Tomko (University of Cincinnati)
Submitted by Samir Das <sdas@ececs.uc.edu>
----------------------------------------------------------------------
PACT'01: International Conference on
Parallel Architectures and Compilation Techniques
NEW early registration deadline: July 25, 2001
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Barcelona, Spain. September 8-12, 2001
http://www.ac.upc.es/pact01
Dear colleague,
Just a reminder that the deadline for advance registration to the 10th
International Conference on Parallel Architectures and Compilation
Techniques PACT'01 is July 25, 2001 (new deadline). PACT'01 will take
place in Barcelona (Spain), September 8-12, 2001.
We strongly suggest that you make your room reservations in advance.
Some of the hotels offered to PACT'01 delegates have the reservation
deadline close (during this month).
Conference: September 10-12
---------------------------
The conference program includes three outstanding keynote speakers:
- Randall D. Isaac (VP Science and Technology, IBM Research)
- Justin Rattner (Intel Fellow and Director of Microprocessor
Research Labs MRL)
- Joel Emer (Compaq Staff Fellow)
26 cutting-edge research papers organized in 9 Technical Sessions and
a special session on:
- Work in Progress: researchers are invited to submit abstracts
of new research and wild ideas by July 13th.
Before the conference, 2 tutorials and 5 workshops will be held on
September 8-9:
Workshops:
----------
Saturday, September 8th
- EWOMP'01 (full day). European Workshop on OpenMP (submission
closed, advance program available)
- WBT'01 (full day). Workshop on Binary Translation (submission
closed).
- MEDEA'01 (morning). Workshop on Memory Access Decoupled
Architectures (submission deadline: July 7, 2001).
Sunday, September 9th
- EWOMP'01 (full day). Continuation from previous day.
- COLP'01 (full day). Workshop on Compilers and Operating Systems
for Low Power (submission deadline: August 1, 2001).
- WUCC'01 (morning). Workshop on Ubiquitous Computing and
Communication (submission closed).
Tutorials:
----------
Saturday, September 8th (afternoon)
- 3G Wireless Infrastructure: Architecture, Algorithms,
and Applications. Allan Berenbaum, Nevin Heintze,
Stefanos Kaxiras and Girija Narlikar.
Sunday, September 9th (afternoon)
- The Design and Implementation of the Jalapeno JVM.
Michael Hind, IBM Research.
For additional information about the conference, the complete advance program
with information about the workshops and tutorials, registration and
accomodation, please vit the conference site located at:
http://www.ac.upc.es/pact01
Submitted by pact2001@ac.upc.es
----------------------------------------------------------------------
MEDEA Workshop
MEmory access DEcoupled Architectures
and related issues
September 8, 2001, Barcelona, Spain
http://www.dii.unisi.it/medea
held in conjuction with
PACT 2001 Conference
September 8-12, 2001, Barcelona, Spain
http://research.ac.upc.es/pact01/
List of Topics
--------------
We solicit papers of original research including, but not
limited to, the following areas:
Memory Access Decoupling
Compiler Based Decoupling
Function Decoupling
Processor Architecture
Latency Tolerance
Instruction Level Parallelism
Thread Level Parallelism
New RAM Architectures
Multithreading
Chip Multiprocessors
Important Dates
---------------
July, 7 2001 Submission Deadline (plus 1 week extension)
July, 25 2001 Acceptance Notification
August, 1 2001 Final Papers Due
September, 8-12 2001 PACT Conference in Barcelona, Spain
Scope and Motivation
--------------------
Most of today's advanced processor architectures are based
on the Superscalar and Multiple Issue paradigm.
These include MIPS-R10000, Power-PC, Ultra-Sparc,
Alpha 21164 and 264, Pentium family.
Research has been developed to exploit Instruction Level
Parallelism (ILP), Branch Prediction, Predicative Execution,
Speculative Loads, VLIW (e.g. Itanium, i.e. IA-64/EPIC),
Multithreaded Approach (Compaq EV8, i.e. Alpha 21464),
and Chip Multiprocessor (CMP, IBM Power4).
This workshop aims to bring up an old idea, Access Decoupling,
in this new arena. We wish to hear from people working in
multithreading, Thread Level Parallelism, ILP, superscalar
processors, novel RAM architectures, memory hierarchy
optimizations, data dependencies optimizations both from
compiler and architectural point of view.
Many research groups have recently revived Access Decoupling
and its now time to show how this paradigm can wide the
spectrum of solutions to overcome the memory-wall problem.
In particular, we'd like to explore new sources for
parallelism.
In this workshop, we wish to put in contact people interested
in evaluating how the old idea of memory access decoupling
could be applied in this new scenario as a viable alternative
to new processor designs.
Organizing Commitee
-------------------
Roberto Giorgi, giorgi@acm.org
University of Siena, Italy
Cosimo Antonio Prete, prete@iet.unipi.it
University of Pisa, Italy
Jelica Protic, jeca@sezampro.yu
University of Belgrade, YU
Submission details
------------------
We only accept electronic submissions in PDF format.
Please format your paper by following the author
guidelines specified in:
http://www.computer.org/cspress/instruct.htm
In brief: authors should provide papers in 8.5x11-inch
IEEE proceedings format. The maximum number of pages
is limited to 6. Please do not use fonts smaller than
10 points.
In case of selection for further publication, authors
may be required to extend their paper.
Submitted by Roberto Giorgi <giorgi@acm.org>
----------------------------------------------------------------------
HOT Chips 13
A Symposium on High-Performance Chips
August 19-21, 2001, Memorial Auditorium
Stanford University, Palo Alto, California
ADVANCE PROGRAM
Hot Chips 13 brings together designers and architects of high-performance
chips, software, and systems. Presentations focus on up-to-the-minute real
developments. This symposium is the primary forum for engineers and researchers
to highlight their leading-edge designs. Three full days of tutorials and
technical sessions will keep you on top of the industry.
Sunday August 19
-----------------
Morning Tutorial Jan Rabaey, UC Berkeley
* Silicon Platforms for the Next-Generation Wireless Systems
Afternoon Tutorial Rob A. Rutenbar, Carnegie Mellon/Neolinear,
Ramesh Harjani, Univ. of Minnesota
* Design at the Leading Edge of Mixed-Signal IC
Monday August 20
------------------
Microprocessors I
* R18000, The latest SGI Superscalar Microprocessor, Silicon Graphics
* The ARM10 family of Embedded Microprocessor Cores, ARM, inc.
* Power4 System Design for High Reliability, IBM
Embedded Solutions
* Embedded Benchmarking w/ an Xtensa Configurable Processor, Tensilica
* SH-5: A First 64-bit SuperH Core with Multimedia Extension, Hitachi
* Gekko: a PPC supporting high-performance 3D graphics, IBM
Keynote: Atiq Raza, Raza Foundries
Silicon for a 10 Gigabit-per-second connected world
Integrated Communications and Networking
* A Mobile Station Modem Chip for WCDMA, Qualcomm
* nFlex, A Broadband Wireless Communications Processor, nBand Comm.
* InfiniBridge: An Integrated InfiniBand Switch/Channel Adapter, Mellanox
High Speed Communications
* Tiny Tera-X: A 2.5Tb/s switch core with LCS interface, PMC-Sierra
* 5 GB/s backplane transceiver, Accelerant Networks
* A Single-Chip Terabit Switch, Velio Comm.
Panel: Moderator: Linley Gwennap, The Linley Group
My network processor is better than your network processor!
Tuesday August 21
------------------
Network Switch Technology
* Fast pattern matching and routing for OC-48, Agere Systems
* Fabr-IC: Single-Chip Gigabit Ethernet Switch w/ Integrated Mem, MOSAID
* Ultra high performance network memory, Alpine Microsys
* Tyrant: A High Performance Storage over IP Switch Engine, Nishan Systems
Storage
* 1.8-inch Super Small Slim HDD, Toshiba
* Microdrive: High Capacity Storage for the Handheld Revolution, IBM
* DataPlay, a New Technology for Information Distribution, DataPlay
Keynote : Mark Dean, IBM Fellow & VP of Systems Research
Trends Impacting Computing Systems Design and the IT Industry
Chip Multiprocessors
* 53 GOPS Programmable Vision Processor, Infineon
* A MIMD-based Multi Threaded Processor, Kirchoff Inst.
* The Raw Processor: A Composeable 32-Bit Fabric, MIT
Microprocessors II
* Itanium Performance Insights from the IMPACT Compiler, Univ. of Illinois
* The Intel 870 Family of Enterprise Chipsets, Intel
* The Pentium 4 Processor, Intel
-----------------------------------------------------------------------
Organizing Committee Program Committee
Chair Lily Jow Compaq Program Co-Chairs
Finance Angela Lee Compaq John Kubiatowicz UC Berkeley
Publicity Cary Kornfeld kDesign Andy Wolfe SONICblue
Vojin Oklobdzija UC Davis
Advertising Allen Baum Compaq Program Committee
Publications Linda McAllister Forest Baskett NEA
David Moberly Agilent Bill Dally Stanford
Registration Joe Fitzgerald Keith Diefendorff ARCCores
Bala Joshi Intel Norm Jouppi Compaq
Alice Young Jim Keller Broadcom
Nicholas Blasgen NetScalar Chuck Moore Parthus Sys
Local Arrag. Amr Zaky ARC Cores Jan Rabaey UC Berkeley
Bob Lashley Sun Howard Sachs HGS Eng.
Yusuf Abdulghani Apple Mitsuo Saito Toshiba
Webmaster Ann Zeise GoMilpitas.com John Shen Intel
At Large Martin Freeman Philips Rsrch Alan Jay Smith UC Berkeley
Slava Mach SCVCS Chair George Taylor
Howard Sachs HGS Eng. Marc Tremblay Sun
Gail Sachs HGS Eng. John Wawrzynek UC Berkeley
Alan Jay Smith UC Berkeley
Bob Stewart SRE
Kimming So Broadcom
This is a preliminary program; changes may occur.
Registration will begin at http://www.hotchips.org after June 1st.
For the most up-to-the-minute details on presentations and schedules,
and for information on registration, please check http://www.hotchips.org.
For registration help, email mailto://registration@hotchips.org.
For general questions, email mailto://info@hotchips.org
Sponsored by the Technical Committee on Microprocessors and Microcomputers
of the IEEE Computer Society
Submitted by Alan Smith <smith@EECS.Berkeley.EDU>
----------------------------------------------------------------------
Removing Yourself from SIGARCH Mailing List
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recorded on the SIGARCH list (no forwarding), you can
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you from the list.
----------------------------------------------------------------------
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