Attached is the SIGARCH mailing list digest for June 2001 (grep sigarch-jun01): * Hot Chips Advanced Program (http://www.hotchips.org) * Workshop on Caching, Coherence and Consistency (WC3 '01) Call for Participation: http://www.cs.rutgers.edu/~wc3/ * Removing yourself from SIGARCH mailing list --Mark D. Hill infodir_SIGARCH@acm.org SIGARCH Information Director P.S. I will be traveling to ISCA so the July digest will not go out until July 6th or so. ---------------------------------------------------------------------- Mark D. Hill Office 6373 CSS Professor & Romnes Fellow Phone 608-262-2196 Computer Sciences Department Asstnt 608-265-3402 University of Wisconsin-Madison FAX 608-262-9777 1210 West Dayton Street E-mail markhill@cs.wisc.edu Madison, WI 53706-1685 USA http://www.cs.wisc.edu/~markhill ---------------------------------------------------------------------- HOT Chips 13 A Symposium on High-Performance Chips August 19-21, 2001, Memorial Auditorium, Stanford University, Palo Alto, California ADVANCED PROGRAM Hot Chips 13 brings together designers and architects of high-performance chips, software, and systems. Presentations focus on up-to-the-minute real developments. This symposium is the primary forum for engineers and researchers to highlight their leading-edge designs. Three full days of tutorials and technical sessions will keep you on top of the industry. Sunday August 19 ----------------- Morning Tutorial Jan Rabaey, UC Berkeley * Silicon Platforms for the Next-Generation Wireless Systems Afternoon Tutorial Rob A. Rutenbar, Carnegie Mellon/Neolinear, Ramesh Harjani, Univ. of Minnesota * Design at the Leading Edge of Mixed-Signal IC Monday August 20 ------------------ Microprocessors I * R18000, The latest SGI Superscalar Microprocessor, Silicon Graphics * The ARM10 family of Embedded Advanced Microprocessor Cores, ARM, inc. * Power4 System Design for High Reliability, IBM Embedded Solutions * Embedded Benchmarking w/ an Xtensa Configurable Processor, Tensilica * SH-5: A First 64-bit SuperH Core with Multimedia Extension, Hitachi * Gekko: a PPC supporting high-performance 3D graphics, IBM Keynote: Atiq Raza, Raza Foundries Silicon for a 10 Gigabit-per-second connected world Integrated Communications and Networking * A Mobile Station Modem Chip for WCDMA, Qualcomm * nFlex, A Broadband Wireless Communications Processor, nBand Comm. * InfiniBridge: An Integrated InfiniBand Switch/Channel Adapter, Mellanox High Speed Communications * Tiny Tera-X: A 2.5Tb/s switch core with LCS interface, PMC-Sierra * 5 GB/s backplane transceiver, Accelerant Networks * A Single-Chip Terabit Switch, Velio Comm. Panel: Moderator: Linley Gwennap, The Linley Group My network processor is better than your network processor! Tuesday August 21 ------------------ Network Switch Technology * Fast pattern matching and routing for OC-48, Agere Systems * Fabr-IC: Single-Chip Gigabit Ethernet Switch w/ Integrated Mem, MOSAID * Ultra high performance network memory, Alpine Microsys * Tyrant: A High Performance Storage over IP Switch Engine, Nishan Systems Storage * 1.8-inch Super Small Slim HDD, Toshiba * Microdrive: High Capacity Storage for the Handheld Revolution, IBM * DataPlay, a New Technology for Information Distribution, DataPlay Keynote : Mark Dean, IBM Fellow & VP of Systems Research Trends Impacting Computing Systems Design and the IT Industry Chip Multiprocessors * 53 GOPS Programmable Vision Processor, Infineon * A MIMD-based Multi Threaded Processor, Kirchoff Inst. * The Raw Processor: A Composeable 32-Bit Fabric, MIT Microprocessors II * Itanium Performance Insights from the IMPACT Compiler, Univ. of Illinois * The Intel 870 Family of Enterprise Chipsets, Intel * The Pentium 4 Processor, Intel ----------------------------------------------------------------------- Organizing Committee Program Committee Chair Lily Jow Compaq Program Co-Chairs Finance Angela Lee Compaq John Kubiatowicz UC Berkeley Publicity Cary Kornfeld kDesign Andy Wolfe SONICblue Vojin Oklobdzija UC Davis Advertising Allen Baum Compaq Program Committee Publications Linda McAllister Forest Baskett NEA David Moberly Agilent Bill Dally Stanford Registration Joe Fitzgerald Keith Diefendorff ARCCores Bala Joshi Intel Norm Jouppi Compaq Alice Young Jim Keller Broadcom Local Arrag. Amr Zaky ARC Cores Chuck Moore Chicory Sys Bob Lashley Sun Jan Rabaey UC Berkeley Yusuf Abdulghani Apple Howard Sachs HGS Eng. Webmaster Ann Zeise GoMilpitas.com Mitsuo Saito Toshiba At Large Martin Freeman Philips Rsrch John Shen Intel Slava Mach SCVCS Chair Alan Jay Smith UC Berkeley Howard Sachs HGS Eng. George Taylor Alan Jay Smith UC Berkeley Marc Tremblay Sun Bob Stewart SRE John Wawrzynek UC Berkeley Kimming So Broadcom This is a preliminary program; changes may occur. Registration will begin at http://www.hotchips.org after June 1st. For the most up-to-the-minute details on presentations and schedules, and for information on registration, please check http://www.hotchips.org. For registration help, email mailto://registration@hotchips.org. For general questions, email mailto://info@hotchips.org Sponsored by the Technical Committee on Microprocessors and Microcomputers of the IEEE Computer Society Submitted by: "Allen J. Baum" <abaum@3wisemonkeys.net> ---------------------------------------------------------------------- CALL FOR PARTICIPATION Workshop on Caching, Coherence and Consistency (WC3 '01) Sorrento, Italy, June 17, 2001 to be held in conjunction with the 2001 ACM International Conference on Supercomputing (ICS '01) URL: http://www.cs.rutgers.edu/~wc3/ email: wc3@cs.rutgers.edu Overview The workshop focuses on three remarkably persistent topics in computer systems research: caching, coherence and consistency. For a long time these topics were associated with parallel and distributed systems only. More recently, caching, coherence and consistency issues are being revisited in the context of mobile computing and the world-wide web. Our goal with this workshop is to provide a forum for researchers from all of these communities to present and exchange ideas on these three topics. Thus, we intend this workshop to cover a range of domains, from more traditional ones such as hardware and software cache coherence schemes and multiprocessor memory consistency models, to coherence and consistency issues in file systems and mobile data, to content caching and consistency issues in replicated data and services on the web. This workshop can be seen as a continuation of the WSDSM workshops that were held in conjunction with the last two ICS conferences but with an extended scope and addressing a significantly broader audience. Advance Program The advance program can be found at http://www.cs.rutgers.edu/~wc3/. WC3 Registration The registration information can be found on the ICS '01 Web page, http://www.cib.na.cnr.it/ics01/. Program Committee Ricardo Bianchini Rutgers University (co-chair) Mark Crovella Boston University Fred Douglis AT&T Babak Falsafi Carnegie Mellon University Mark Heinrich Cornell University Liviu Iftode Rutgers University (co-chair) Pete Keleher University of Maryland Bruce Maggs Carnegie Mellon University Christine Morin IRISA, France Amin Vahdat Duke University Workshop Organizers Ricardo Bianchini and Liviu Iftode Department of Computer Science Rutgers University Piscataway, NJ 08854-8019 E-mail: {ricardob,iftode}@cs.rutgers.edu Submitted by Ricardo Bianchini & Liviu Iftode <{ricardob,iftode}@cs.rutgers.edu> ---------------------------------------------------------------------- Removing Yourself from SIGARCH Mailing List If your email address exactly matches the email address recorded on the SIGARCH list (no forwarding), you can remove yourself with: mail listserv@acm.org with message body (not subject): unsubscribe SIGARCH-MEMBERS If your email address does *not* match, mail me at infodir_SIGARCH@acm.org, and I will work to remove you from the list. ---------------------------------------------------------------------- ----------------------------------------------------------------------