[Gems-users] Question about MOESI-CMP-directory

[Hamid Reza Khaleghzadeh <khaleghzadeh@xxxxxxxxx>]

Hi

I am using Simics and Gems 2.1 for running my applications. I have
simulated a eight cores processor that contains 4 chips. Following
schema shows my simulated machine:

Core0     Core1     Core2     Core3     Core4     Core5     Core6     Core7
    |------------|             |-------------|
|------------|              |------------|
          |                           |                          |
                      |
         L2                        L2                       L2
                L2
          |---------------------------|--------------------------|---------------------------|
                                                   |
                                               Memory
-Each core has a private DL1 and IL1 cache and coherency protocol is MOESI.

I have run following application on the simulated machine:

for (i=0;i<5;i++)
{
      THREAD1;     // thread1 write into a large array. Size of the
array is smaller than L2 cache.
      THREAD2;    // thread2 read filled array by thread1
}


I have faced with a strange result. This application have been
executed on the simulated machine two times, First, on cores 2, 3 then
on cores 2 and 4. I found that number of L2 miss of first run is
bigger than second one. But I think number of miss of second run must
be more than first one because in the second run, number of
Invalidations are bigger than first one. Could you tell me how you
legitimise this? Is it possible MOESI-CMP-directory was not
implemented correctly?

--
Hamid Reza Khaleghzadeh