[Gems-users] Question about coherency protocol

[Hamid Reza Khaleghzadeh <khaleghzadeh@xxxxxxxxx>]

Hi

I have defined a multi-core processor that consist of two chips and each chip has two processors. Each chip contains one L2 cache. Could you tell me there are any connections between L1's of chip0 with L1's of chip1 directly? In other word, Suppose a block is written by a core that exists in chip0. when this block want to be read by a core that exists in chip1, Is the block read via L2 of chip0 or can be read from L1 of chip0 directly?

Thanks.