Re: [Gems-users] Only read request catched when tracing memory request

[Dan Gibson <degibson@xxxxxxxx>]

Write requests will only show up at the memory controller when the L2 evicts a dirty line. The L2 will only evict a dirty line when the L2 is nearly full -- and even then writebacks are rarer than demand reads. This is why write-back caches are fairly efficient -- they enable a lot of write-combining and write-deferral.

Regards,
Dan

On Tue, Apr 6, 2010 at 5:22 AM, Xing Zhang <zxj.xing@xxxxxxxxx> wrote:

Hi Byn,

 

Thank you for reply.

 

You're right. I checked the cache size. To my geat surprise, the default L2 cache size is set to 16 megabytes. After setting it to 256K, I did got the write request.

 

But i still have a question. In the trace file, the ratio of write requests to total becomes smaller while cache size is set bigger. With 16 megabytes of cache size, there is even no write request, but still read request. How to explain it?

 

Thank you again.

 

Xing

2010/4/6 Byn Choi <bynchoi1@xxxxxxxxxxxx>

My guess is either or both:

1. Caches are too big.
2. Simulation didn't run for long enough.

So that, in the end, there wasn't any writeback requests issued down to the memory controller. Just as a sanity check, try running it for a while with really small caches.

Byn

On Apr 5, 2010, at 8:16 PM, Xing Zhang wrote:

Hi,

I want to get memory access trace of memory subsystem. I did it by adding some code to issueRequest in MemoryControl.c(ruby/system). The MemoryConrol.[hC] models memory controller component, I think it's the right place to trace memory request. But the result turned out what I got were only memory Read requests, none Write request.

Does anyone know  why? Is there anything wrong?

Thanks in advance.

Xing

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