Re: [Gems-users] Only read request catched when tracing memory request

[Byn Choi <bynchoi1@xxxxxxxxxxxx>]

My guess is either or both:

1. Caches are too big.
2. Simulation didn't run for long enough.

So that, in the end, there wasn't any writeback requests issued down  
to the memory controller. Just as a sanity check, try running it for a  
while with really small caches.
Byn

On Apr 5, 2010, at 8:16 PM, Xing Zhang wrote:

> Hi,
>
> I want to get memory access trace of memory subsystem. I did it by  
> adding some code to issueRequest in MemoryControl.c(ruby/system).  
> The MemoryConrol.[hC] models memory controller component, I think  
> it's the right place to trace memory request. But the result turned  
> out what I got were only memory Read requests, none Write request.
> Does anyone know  why? Is there anything wrong?
>
> Thanks in advance.
>
> Xing
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