Re: [Gems-users] cache reference and its associated processor id

["Carole-Jean Wu" <carolewu@xxxxxxxxxxxxx>]

Hello!!!

I found what I am missing!

In RubySlicc_Exports.sm, Type Address has to be modified to have the additional methods as well!

-Carole

;-)

On Sat, Oct 18, 2008 at 9:52 PM, Jayaram Bobba <bobba@xxxxxxxxxxx> wrote:

Have you tried 'make clean' and then 'make'?

Carole-Jean Wu wrote:
> Thanks for your reply, Jayaram.
>
> I added an extra field for Address.h. Now Address has two private
> fields, one is physical_address_t m_address and the other is MachineID
> proc_id. I also implemented the set and get methods in class Address.
> Then I modified my -L1cache.sm as follows:
>
> In about line 410:
>
> //Actions
> .
> .
> .
> out_msg.Address = address;
> out_msg.Address.setPid(machineID); ---> I added this line
> .
> .
> .
>
> And when I make my protocol, I get error message:
>
>
> ../protocols/MSI_MOSI_CMP_
> directory-L1cache.sm:410: Error: Invalid method call: Type 'Address'
> does not have a method 'setPid_MachineID'
> make[1]: *** [generated/MSI_MOSI_CMP_directory/generated] Error 1
>
> I am suspecting that when the generated code is generated with the .sm
> files, it did not re-check the modifed sources. Do you have any ideas
> how this can be fixed?
>
>
> Thanks in advance!
> Carole
>
>
> On Sat, Oct 18, 2008 at 8:50 PM, Jayaram Bobba <bobba@xxxxxxxxxxx

> <mailto:bobba@xxxxxxxxxxx>> wrote:
>
>     Look for the "Requestor" field in RequestMsg in *-msg.sm

>     <http://msg.sm>

>     If that is not the info you need, you could add a field
>     to the structure and set it while initializing an L2 request
>     in *-L1cache.sm
>     If you need to pass info from sequencer to L1, add a field to CacheMsg
>     in RubySlicc_Exports.sm and set it while initializing a cache request
>     in SimicsProcessor.C
>
>
>     Carole-Jean Wu wrote:
>     > Hello,
>     >
>     > I have a 16-core CMP system setup with private L1 caches and a
>     shared
>     > L2 cache, and I would like to have information about which core a
>     > memory reference in L2 is issued. Does anyone know how I can get
>     this
>     > information? Even knowing how to get the m_version of the associated
>     > L1's sequencer will help.
>     >
>     >
>     > Thanks in advance!
>     > Carole
>     >
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