Re: [Gems-users] cache reference and its associated processor id

[Jayaram Bobba <bobba@xxxxxxxxxxx>]

Look for the "Requestor" field in RequestMsg in *-msg.sm
If that is not the info you need, you could add a field
to the structure and set it while initializing an L2 request
in *-L1cache.sm
If you need to pass info from sequencer to L1, add a field to CacheMsg
in RubySlicc_Exports.sm and set it while initializing a cache request
in SimicsProcessor.C


Carole-Jean Wu wrote:
> Hello,
>
> I have a 16-core CMP system setup with private L1 caches and a shared 
> L2 cache, and I would like to have information about which core a 
> memory reference in L2 is issued. Does anyone know how I can get this 
> information? Even knowing how to get the m_version of the associated 
> L1's sequencer will help.
>
> Thanks in advance!
> Carole
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