Re: [Gems-users] SM/OM state in MOESI protocol

[huangh@xxxxxxxxx]

>
> Suppose P1 issued a load to a block, and the load has already had the data
> (from either other cache or memory), and the load instruction hasn't been
> committed inside P1, in this period, other processor issues a store to the
> same block, there would be a invalidation arrived in P1's cache, then how
> does P1 handle this case? Or if the sequencer doesn't allow this
> situation?
>
> I think it is related to memory model, and I also want to know which
> memory
> model does GEMS implement?

This definitely defined by memory model of your system.

Suppose load1 is before load2 in program order, and load1 is not issued
(for example load1 just enter LSQ after register renaming stage),
following situations may occur:
1) Load2 hits in D$ and load2 doesn't write back (it is say the
instructions which are after load2 in program order and depend on load2
have not use load2 result);

2) Load2 hits in D$ and load2 has written back its result to register file
(so following instructions which depend on load2 may consume its result);

At this time, if an invalidation command fired by another core's store
instruction conflicts with load2's address, how to handle above two
situations? I think this depends on the memory model of your system. Weak
ordering or processor consistency have different requirement.




Huang He