On Sun, Nov 23, 2008 at 12:30 AM, Xuehai Qian
<xuehaiq@xxxxxxxxx> wrote:
Hi Everyone,
I would like to know why in SM/OM state, if the processor issues a load, it can be considered as hit, and load can use the old copy? Because there should be an outstanding store to the same location before the load, and the load should get the new data, instead of the old copy. In MESI protocol, I noticed that SM cannot service load, which is reasonable. Can anyone help me? Thanks!
I don't think the transition will ever happen...making it hit might be a mistake.
In-order processor models (i.e., just Simics) will never issue multiple memory references for the same block.
When using the Opal out-of-order processor model, I think the Ruby sequencer might still prevent two outstanding accesses for the same block. But I'm not sure.
--Mike
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