[Gems-users] flushing L1 caches

[Mladen Nikitovic <mladen@xxxxxx>]

Hi,

I'm trying to implement a function that flushes the L1 caches.  You can 
see from my previous posts that I have arrived at a solution that 
involves some augmentation of protocol code etc. But, the final thing is 
actually implementing the flush in the Sequencer, which was supposed to 
be done be walking the I and D-cache entries and sending invalidation 
request via the mandatory queue. I have tried to do that but the 
simulation crashes when I try call the flush at the point of shutting 
down one of the processors.
Implementation-wise, is there anything in the following function that 
should change?
Thanks.

Regards,
Mladen

void Sequencer::flushL1caches(int cpu)
{
 Time latency = SEQUENCER_TO_CONTROLLER_LATENCY;
 CacheMsg Imsg, Dmsg;
 int i,j, Iassoc, Dassoc, Isets, Dsets;

 Imsg.setType(CacheRequestType_INVALIDATE);
 Dmsg.setType(CacheRequestType_INVALIDATE);

 Isets = 
m_chip_ptr->m_L1Cache_L1IcacheMemory_vec[m_version]->getCacheNumSets();
 Dsets = 
m_chip_ptr->m_L1Cache_L1DcacheMemory_vec[m_version]->getCacheNumSets();
 Iassoc = 
m_chip_ptr->m_L1Cache_L1IcacheMemory_vec[m_version]->getCacheAssoc();
 Dassoc = 
m_chip_ptr->m_L1Cache_L1DcacheMemory_vec[m_version]->getCacheAssoc();
 for(i=0; i<Isets; i++) {
   for(j=0; i<Iassoc; j++) {
     
Imsg.setAddress(m_chip_ptr->m_L1Cache_L1IcacheMemory_vec[m_version]->getAddress(i,j)); 

     m_chip_ptr->m_L1Cache_mandatoryQueue_vec[m_version]->enqueue(Imsg, 
latency);
   }
 }

 for(i=0; i<Dsets; i++) {
   for(j=0; i<Dassoc; j++) {
     
Dmsg.setAddress(m_chip_ptr->m_L1Cache_L1DcacheMemory_vec[m_version]->getAddress(i,j)); 

     m_chip_ptr->m_L1Cache_mandatoryQueue_vec[m_version]->enqueue(Dmsg, 
latency);
   }
 }
}