I am using GEMS to simulate a single-chip CMP system. I tried to use
the MESI_SCMP_tiledL2bank_directory protocol, but I don't quite
understand how to set up the network file to support different
configurations (e.g., with 2 cores, 4 cores, etc.).
GEMS 1.4 release only includes one file:
TILED_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
I tried to modify it for a simple two-core system:
---------------------------------------------------------------------------------------
processors:2
procs_per_chip:2
L2banks:2
memories:2
ext_node:L1Cache:0 int_node:0 link_latency:1 bw_multiplier:72
ext_node:L2Cache:0 int_node:0 link_latency:1 bw_multiplier:72
ext_node:L1Cache:1 int_node:1 link_latency:1 bw_multiplier:72
ext_node:L2Cache:1 int_node:1 link_latency:1 bw_multiplier:72
ext_node:Directory:0 int_node:0 link_latency:1 bw_multiplier:80
ext_node:Directory:1 int_node:1 link_latency:1 bw_multiplier:80
int_node:0 int_node:1 link_latency:2 bw_multiplier:64
-------------------------------------------------------------------------------------------
I'll try this on my end and get back to you
Could you help clarify how to set up the network file or provide the
correct configuration? Is it possible to use other network topology
like PT_TO_PT? I couldn't find detailed document on this.
PT_TO_PT should run, but not as realistic.
Also, is there any other protocol available for simulating single-chip
CMP? It seems the only one available now is
MESI_SCMP_tiledL2bank_directory.
Sure, you can use MSI_MOSI_CMP_directory or MOESI_CMP_directory. Just
set the PROCS_PER_CHIP to the same number of processors. But since
these protocols support hierarchical coherence, they are more complex
than needed for a Single-CMP
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