Re: [Gems-users] question on assertions in setState() of MOESI_SMP_directory

["hongxia sun" <sunhx.seraph@xxxxxxxxx>]

Hi,

 

I have added a writeback_buffer/victim_buffer between L1 cache and L2 cache. You can implement a victim_cache class as CacheMemory.h does. And then instantiate it in your Protocol.sm . Pay attention, states and transitions need to be modiefied because a cache miss firstly need to check the victim buffer and a replacement firsty need to put into victim buffer. Moreover, you need to add a queue such as mandatory queue (you can use the optional queue) to transfer messages between cache and your victim buffer.

 

Best Regards,

 

Hongxia SUN

 

2007/2/9, Liqun Cheng <liqun.cheng@xxxxxxxxx>:

Hi,

I am confused about the three assertations in getState() of MOESI_SMP_directory- cache.sm. Does MOESI_SMP_directory use exclusive cache hierarhcy? If so, how about the self-modified codes. These will show up in both L1D and L1I, right?
/*** assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent (addr)) == false);
      assert((L1IcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
      assert((L1DcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);   ***/

Another question is that I plan to add a RAC, used as a victim cache for remote date. What's the easiest way to do this? Do I have to walk through the whole .sm file to check every transition?

thanks!
Legion

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