Re: [Gems-users] question on assertions in setState() of MOESI_SMP_directory

[Mike Marty <mikem@xxxxxxxxxxx>]

> I am confused about the three assertations in getState() of
> MOESI_SMP_directory-cache.sm. Does MOESI_SMP_directory use exclusive cache
> hierarhcy? If so, how about the self-modified codes. These will show up in
> both L1D and L1I, right?
> /*** assert((L1DcacheMemory.isTagPresent(addr) &&
> L1IcacheMemory.isTagPresent(addr)) == false);
>       assert((L1IcacheMemory.isTagPresent(addr) &&
> L2cacheMemory.isTagPresent(addr)) == false);
>       assert((L1DcacheMemory.isTagPresent(addr) &&
> L2cacheMemory.isTagPresent(addr)) == false);   ***/
>

Yes, we enforce exclusion between L1I and L1D caches.  If instructions are
modified, they are replaced to the L2 cache and then fetched into the L1D
cache.

> Another question is that I plan to add a RAC, used as a victim cache for
> remote date. What's the easiest way to do this? Do I have to walk through
> the whole .sm file to check every transition?
>

You can either incorporate this cache into an existing controller (similar
to how the SMP protocols use a combined L1/L2 controller), or create a
seperate controller.

--Mike