Hi Dan,
Unfortunately, I think we do need to know the data that resides in the cache...
Our project sounds similar to the post here:
https://lists.cs.wisc.edu/archive/gems-users/2006-October/msg00008.shtml
> we would like to simulate a system in which there
> might be several different speculative values for the same address, on
> different cache controllers. Obviously, this can not be directly implemented
> in Simics, due to the single global memory image. The different values
> should be held on the Ruby caches
A few possibilities:
1) Is there a version of Ruby that supports the DataBlk?
2) How hard would it be to change the cache structure to once again support the DataBlk. I'm guessing fairly hard, but I'd like your opinion.
3) In a non-transactional memory protocol, does the variable m_XactMemory help to store the data values at all? I saw a post which referenced this, but I didn't understand it very well.
4) Do you have any other ideas?
Thanks so much!
Rob, Brianna, and Liz
---- Original message ----
>Date: Sat, 21 Apr 2007 22:15:14 -0500
>From: Dan Gibson <degibson@xxxxxxxx>
>Subject: Re: [Gems-users] Ruby DataBlock
>To: Gems Users <gems-users@xxxxxxxxxxx>
>
>Do you need to know the data that resides in the cache, or do you need
>to know the *correct* value of the data at a given moment?
>The latter can be obtained by the SIMICS_read_physical_memory() API. The
>former will require reviving the somewhat deprecated DATA_BLOCK flag...
>I'm not sure who to ask about that.
>
>Regards,
>Dan
>
>Robert William Havlik wrote:
>
>>Hello,
>> I am trying to look at the data values within the cache lines with Ruby. When I try to set DATA_BLOCK to true in rubyconfig.defaults, I get the following error when I run anything:
>>
>>failed assertion 'SIMICS_check_memory_value(m_proc, mem_trans->s.physical_address, buffer, mem_trans->s.size)' at fn void SimicsProcessor::observeMemoryAccess(memory_transaction_t*) in simics/SimicsProcessor.C:493
>>failed assertion 'SIMICS_check_memory_value(m_proc, mem_trans->s.physical_address, buffer, mem_trans->s.size)' at fn void SimicsProcessor::observeMemoryAccess(memory_transaction_t*) in simics/SimicsProcessor.C:493
>>At this point you might want to attach a debug to the running and get to the
>>crash site; otherwise press enter to continue
>>PID: 15562
>>
>>When I looked at some of the other forum posts, I decided to try commenting the assert that fails above, when I comment this, I get:
>>
>>[cpu0 info] Got exception 0x34 at (MAXTL - 1) - entering RED_state
>>Write to unimplemented ASI 0x60, VA 0x0, data 0x0
>>[cpu0 info] Got exception 0x32 at MAXTL - entering error_state
>>[cpu0 info] Triggering watchdog reset to end error_state
>>error_state entered
>>[cpu0] v:0xfffffffff0000040 p:0x7fff0000040 stxa %g0, [%g0 + %g0] 0x60 # ASI_IIU_INST_TRAP
>>
>>Does anyone have any ideas to get the DATA_BLOCK setting to work, or know of another way to look at the data within a cache line. Thanks!
>>
>> -Rob
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>>
>>
>>
>>
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