Re: [Gems-users] ruby results

[Yuho Jin <yuho@xxxxxxxxxxx>]

Hi,

While reading Luke's message, I have one question.

Do MSI_MOSI_CMP_directory and MOESI_CMP_directory
protocols assume a private L2 cache for each processor?
GEMS-wiki says that MSI_MOSI_CMP_directory assumes a shared L2
cache.
Does CMP_NUCA protocol only support a shared L2 cache?
Please, correct me if I misunderstand.

Thanks,
Yuho

On Wed, 13 Sep 2006, Luke Yen wrote:

> Hi,
>
> > So, I draw two conclusions: First, it's not possible
> > to simulate more than 1 processor per chip using SMP
> > protocols. So, I can't get ruby results based on per
> > processor as long as I use MOESI_SMP_hammer or any SMP
> > protocol. I would like to simulate a dual-core
> > machine, similar to dual-core AMD Opteron. That's why
> > I'm using MOESI_SMP_hammer. Second, I still don't
>
>      If you want to model a shared L2 cache like our CMP protocols you
> have to use different cache mapping functions and different virtual
> network connections.  It might be easier to try to split up the file into 2
> different files, one controlling the L1 and one controlling the L2 (like
> for our CMP protocols).
>
>     Otherwise if you want to model private L1 and L2 caches I believe you
> just use the standard-CMP file instead of standard-SMP file in the .slicc
> file for the protocol to get rid of the assertion error.
>
> > understand why my results are always zero for the
> > second processor.
> >
>      Alot of our profiling functions take in machineID numbers, so make
> sure the right number is passed in for the right processor.  You can also
> look at the generated SLICC code to help see this.
>
>   Luke
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