Re: [Gems-users] L2 cache

[Mike Marty <mikem@xxxxxxxxxxx>]

The way the parameters are currently setup, each L2 cache per CMP is
shared and split into banks (controllers) controlled by
g_NUM_L2_BANKS_PER_CHIP.  The g_NUM_L2_BANKS_PER_CHIP_BITS is just the
log2 of that.  The latter should be set automatically based on the former.

--Mike


> Thanks for the help.
> What does the  g_NUM_L2_BANKS_PER_CHIP_BITS means?
>
> Shachar
>
> -----Original Message-----
> From: gems-users-bounces@xxxxxxxxxxx [mailto:gems-users-bounces@xxxxxxxxxxx]
> On Behalf Of Greg Byrd
> Sent: Tuesday, November 21, 2006 4:15 PM
> To: Gems Users
> Subject: Re: [Gems-users] L2 cache
>
> It is a shared L2.  It's just that there are four L2 banks on the chip.
>
> You can control the number of banks (I think) with the
> g_NUM_L2_BANKS_PER_CHIP and g_NUM_L2_BANKS_PER_CHIP_BITS global variables in
> rubyconfig.defaults.
>
> ...gb
>
>
> Shachar Gang wrote:
> > Hi,
> >
> > I am working with MSI_MOSI_CMP_directory protocol with the
> > configuration of four processors per chip.
> > I started a simulation with four Processors (which means only 1 chip)
> > and dump the cache.
> >
> > I found out that I have four L2 caches instead of only one that I
> > expected to have.
> >
> > Where should I config ruby to work with Shared L2 cache in this setup?
> >
> > Shachar Gang
> >
> > --
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