[Gems-users] L2 cache

["Shachar Gang" <shacharg@xxxxxxxxxxxxx>]

Hi,

I am working with MSI_MOSI_CMP_directory protocol with the configuration of
four processors per chip.
I started a simulation with four Processors (which means only 1 chip) and dump
the cache.

I found out that I have four L2 caches instead of only one that I expected to
have.

Where should I config ruby to work with Shared L2 cache in this setup?

Shachar Gang

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