Re: [Gems-users] CPU accesses to L2 cache

["Daniele Bordes" <daniele.bordes@xxxxxxxxx>]

Thank you for your quick reply, Dan.
Here are some statistics for OCEAN case (4 threads bounded on CPUs 1,
3, 5, 7). So CPU0 has no threads scheduled. The simulated system has 8
processors.

total_misses: 876507 [ 189265 94178 38749 80513 249208 87753 53463 83378 ]

Number of L2Hits:

CPU0:  1097866
CPU1:     76340
CPU2:     31702
CPU3:     80534
CPU4:     70295
CPU5:     78558
   (...)

Number of CPU0s accesses is much greater then other CPUs