Re: [Gems-users] Ruby x86 patch

[adgg1@xxxxxxxxx]

Mensaje citado por Dan Gibson <degibson@xxxxxxxx>:

Hello

The main problem is in total_misses I only get stats for 1st processors in x86.
I used default parameters, I only set mem size and number of processors (as the
quickstart guide says). I tried 2 and 4 procs configs and several protocols, and
I always got 0 values for non 1st processors.
I do the same with sparc and values are correct.
I think this was a bug, but I will recheck.

Thanks you so much.

> Hello!
> 
> SPARC's memory_transaction structure (passed to Ruby from Simics) contains 
> a pre-decoded variable for determining if an access is privileged.  x86's 
> structs have a great number of access types defined, in lieu of the single 
> bit from SPARC. Each of these access types may be handled differently if 
> you wish. The "vanilla" version that the x86 patch uses simply treats 
> (nearly) all accesses as non-privileged.
> 
> To change operations from priv to non-priv or vice versa, modify the switch 
> statement in function SIMICS_is_priv_x86 in ruby/simics/interface.C.
> 
> As for your other problems, if you can give some specific information (eg 
> Ruby configuration parameters, if you have changed the defaults and/or 
> simulation error outputs), I will try to reproduce your problems.
> 
> Regards,
> Dan
> 
> At 11:49 AM 10/21/2005 +0200, you wrote:
> 
> >I have tested x86 ruby module, with several configurations (2 & 4 procs), 
> >and I
> >obtained courious results. Only 1st. processor misses, no supervisor mode
> >accesses, no messages for chips others than 1st.
> >
> >Here is a stats file extract:
> >...
> >Total_misses: 9864
> >total_misses: 9864 [ 9864 0 ]
> >user_misses: 9864 [ 9864 0 ]
> >supervisor_misses: 0 [ 0 0 ]
> >
> >instruction_executed: 88731013 [ 41394406 47336607 ]
> >cycles_per_instruction: 0.533477 [ 0.571768 0.499994 ]
> >misses_per_thousand_instructions: 0.111167 [ 0.238293 0 ]
> >.....
> >   L1D_cache_access_mode_type_UserMode:   143677    100%
> >...
> >MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:143677 
> >full:0
> >MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
> >.....
> >
> >I repeated tests with sparc ruby module and I think results are OK. The 
> >extract
> >from stats file:
> >....
> >Total_misses: 19120
> >total_misses: 19120 [ 14741 4379 ]
> >user_misses: 5209 [ 4125 1084 ]
> >supervisor_misses: 13911 [ 10616 3295 ]
> >
> >instruction_executed: 32813149 [ 15066729 17746420 ]
> >cycles_per_instruction: 0.676977 [ 0.737179 0.625866 ]
> >misses_per_thousand_instructions: 0.582693 [ 0.978381 0.246754 ]
> >.....
> >
> >Is this due to x86 beta version?
> >
> >Thanks
> >
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