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SIGARCH-MSG: July 2004 Digest of SIGARCH Messages
This is the July 2004 Digest of SIGARCH Messages (sigarch-jul04):
* Acceptance Rates and Program Committee Memberships for Selected Architecture Conferences
http://www.cs.wisc.edu/~markhill/AcceptanceRates_and_PCs.xls
Submitted by Mark D. Hill <markhill@cs.wisc.edu>
* HotChips 16 Advance Program
http://www.hotchips.org
Submitted by Alan Smith <smith@eecs.berkeley.edu>
* Call for Participation for ASPLOS XI
http://www.eecg.toronto.edu/asplos2004
Submitted by Shubu Mukherjee <shubu.mukherjee@intel.com>
* ISCA 2005 Call for Papers and Call for Tutorial/Workshop Proposals
http://www.cs.wisc.edu/~isca2005/
Submitted by Craig Zilles <zilles@cs.uiuc.edu>
* Call for Papers, The Wild and Crazy Ideas Session IV
http://www.cs.utexas.edu/users/skeckler/wild04
Submitted by Steve Keckler <skeckler@cs.utexas.edu>
* Call for Workshop and Tutorial Proposals for HPCA-11
http://www.hpcaconf.org/hpca11
Submitted by Jared Stark <jared.w.stark@intel.com>
* JILP Call for Predictors (Branch Predictor Competition)
website: http://www.jilp.org/cbp
Submitted by Jared Stark <jared.w.stark@intel.com>
* Second Value-Prediction and Value-Based Optimization Workshop Call for Papers
http://www.csl.cornell.edu/VPW2/
Submitted by Martin Burtscher <burtscher@csl.cornell.edu>
* Workshop on Workload Characterization Call for Papers
http://www.ece.utexas.edu/~ljohn/wwc/
Submitted by Tao Li <taoli@ece.ufl.edu>
* 2004 OASIS Workshop - Call for Papers
http://www.research.ibm.com/actc/OASIS-2004/
Submitted by Jason Nieh <nieh@cs.columbia.edu>
* Call for Participation - SCOPES 2004 Amsterdam, The Netherlands
http://www.scopes2004.org/registration.html
Submitted by Marianne Dalmolen <marianne@ace.nl>
* New papers published online by Computer Architecture Letters
http://www.comp-arch-letters.org/2004paps.html
Submitted by Kevin Skadron <skadron@cs.virginia.edu>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org
* Archive: http://www.cs.wisc.edu/~lists/archive/sigarch-members/maillist.html
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail listserv@acm.org with message body: unsubscribe SIGARCH-MEMBERS
-----------------------------------------------------------------
Doug Burger Office: 3.432 ACES
Assistant Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
The University of Texas at Austin Fax: 512-232-1413
1 University Station, #C0500 E-mail: dburger@cs.utexas.edu
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* Acceptance Rates and Program Committee Memberships for Selected Architecture Conferences
Carrie Pritchard, Mark Hill, Guri Sohi, and David Wood
http://www.cs.wisc.edu/~markhill/AcceptanceRates_and_PCs.xls
When preparing tenure cases and forming program committees, it is
often useful to know the acceptance rates (sheet 1) and program
committee memberships (sheet 2) of ISCA, MICRO, ASPLOS, and HPCA.
Since Carrie Pritchard has typed this information into an excel
workbook, we thought we could save replicated effort by making it
available on the web.
The workbook can also be found off Mark Hill's home page:
http://www.cs.wisc.edu/~markhill > Web Docs > Tools and Data.
----------------------------------------------------------------------
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* HotChips 16 Advance Program
HotChips 16 Advance Program
and Registration Information
Sunday, August 22, 2004
8:30-12:00 Morning Tutorial
Ultrawideband; Technology and Issues
Roberto Aiello Staccato Communications
Anuj Batra Texas Instruments
Sandeep Kumar Adimos
plus others To Be Announced
This tutorial delves into the major issues surrounding the emerging UWB
environment. We discuss some of the fundamental technology issues of this
PHY in both the analog and digital domains. This topic is elaborated using
real world designs to consider the key system level issues that manifest in
UWB based designs. We follow the technology discussions with target market
descriptions and explore the opportunities that UWB technologies enable. Our
discussions are hosted by the drivers behind UWB, system architects and chip
implementers. They describe and discuss the tradeoffs that they faced during
their development of the UWB specs and the initial implementations.
12:00- 1:30 lunch
1:30- 5:00 Afternoon Tutorial
Performance Comparison of State-of-the-Art Volatile and Non-Volatile
Memory Devices
J. Thomas Pawlowski Micron Technology
Between vendor vested interests, presentation hype and datasheet
specsmanship, it is often difficult to determine which memory devices are
truly the most appropriate for an application in question. This is true for
both volatile (DRAM, SRAM and pseudo-SRAM) and non-volatile (NOR and NAND
FLASH) memory devices. This 3 hour tutorial will objectively examine the
memories available today and in the reasonably near future, including SRAMs
such as QDR II, DDR II and QDR III; DRAMs such as DDR2, GDDR3, FCRAM, RLDRAM
and XDR, low-power volatile memory devices such as LPDRAM and PSRAM, and
low-power non-volatile memory devices such as NOR and NAND FLASH. A brief
description will be made concerning external operation of the major devices
and where necessary some description of internal operation. The devices will
be compared by performance (usable bandwidth under various operating
scenarios, energy usage under these scenarios and signal count). Example
operating scenarios include random operations, streaming requests with
defined read/write ratios and resource predictability, streaming requests
with defined read/write ratios but no predictable resource availability,
etc. Performance comparisons are made using a cycle-accurate memory
comparison software tool written by the author and empirically verified.
Cost factors will be considered, including silicon area and test cost of
competing architectures. A brief attempt will be made to assess market size
and dynamics of the major devices where possible. Conclusions will be drawn
for each major operating scenario concerning performance/cost ratios.
Wherever possible, practical application examples will be illustrated to
make the operating scenarios relevant to the system design tasks faced today
and in the reasonably near future.
As Senior Director of Architecture Development in Micron's NetCom Group,
J. Thomas Pawlowski is responsible for Micron memory product definition for
networking and communications applications including products built on DRAM
and FLASH processes. During his tenure at Micron, Thomas has created or
co-created the following DRAM and SRAM devices: reduced latency DRAM II
(RLDRAM II); pipelined, burst, synchronous SRAM (used in Pentium® and
PowerPC® systems); Zero Bus Turnaround. (ZBT®) SRAM (used in network and
communication systems); Double Data Rate (DDR) SRAM; and Quad Data Rate
(QDR) SRAM (versions I, II, and III). Thomas holds over 70 U.S. and
international patents with more pending.
Monday, August 23, 2004
8:30- 8:40 Welcome, Opening Remarks
General Chair: Robert Lashley
Program Co-Chairs: Bill Dally, Keith Diefendorff
8:40-10:10 Session 1: Mobile Processing
Bulverde - An Applications Processor for Phone and PDA Applications
Nigel Paver - Intel
SC10: A Video Processor and Pixel Shading GPU For Handheld Devices
Edward Hutchins - NVIDIA
SH-Mobile3: Application Processor for 3G Cellular Phones on a Low-Power
SoC Design Platform Hiroyuki Mizuno - Hitachi
10:10-10:30 Break
10:30-11:30 Keynote: Robert Denise (JPL)
Mars Exploration Rovers -- a View from the Inside
11:30-12:30 Session 2: High-End Audio and Video
Quartet: A Pipeline-Interleaved Multithreaded Audio DSP
Carl Wakeland, Tom Savell - Creative Labs
CS7050 High Performance H.264/AVC Hardware Video Decoder Core for
Multimedia SOC's Jill Cush - Amphion Semiconductor
12:30- 1:30 Lunch
1:30- 2:30 Session 3: Wireless Communication
IEEE802.11a Based Wireless AV Module with Digital AV Interface
Takashi Wakutsu - Toshiba
Single Chip CMOS Direct Conversion Transceivers for WWAN and WLAN
Tajinder Manku - Sirific Wireless
2:30- 2:50 Break
2:50- 4:20 Session 4: Media and Graphics Processing
The GeForce 6800 GPU John Montrym, Henry Moreton - NVIDIA
New Media Architecture for Next Generation Application Processors
Gerard Williams - ARM
The MXP5800 Media Processor Lou Lippincott - Intel
4:20- 4:50 Break
4:50- 6:20 Session 5: Enabling Technology
Simnow: An Extremely Fast and Accurate Platform and Processor Simulator
Robert Bedichek - AMD
Microchannel Liquid Cooling Solutions
Mark Munch, Jim Hom, Girish Upadhya, Peng Zhou- Cooligy
A New System-On-Chip Bus Architecture Optimized for 1GHz MIPS Processors
John Kinsel, Anna Chiang - PMC-Sierra
6:20- 7:30 Dinner
7:30- 9:30 Panel: Outsourcing Engineering Development Offshore
Moderator: John Nickolls NVIDIA
Panelists: Vinod Dham NewPath Ventures
Ron Hira IEEE-USA, Rochester Inst. Technology
Carl Everett Accel Partners
plus others To Be Announced
Tuesday, August 24, 2004
8:40-10:10 Session 6: Potpourri
MDGRAPE-3 chip: A 165-Gflops application-specific LSI for molecular
dynamics simulations Makoto Taiji - RIKEN
Accelerating Next-Generation Public-key Cryptography on General-Purpose
CPUs Hans Eberle - Sun
How SolarFlare Communications broke the 10Gbps on UTP barrier
Ron Cates - SolarFlare
10:10-10:30 Break
10:30-11:30 Keynote: Steve Jurvetson (Draper Fisher Jurvetson)
Nanotech and the Future of Moore's Law
11:30-12:30 Session 7: Embedded Systems
A Fast Powertrain Microcontroller Erik Norden - Infineon
The Mote Revolution: Low Power Wireless Sensor Network Devices
Joseph Polastre - UC Berkeley
12:30- 1:30 Lunch
1:30- 2:30 Session 8: Low-Power Processors
A 90nm embedded DRAM single chip LSI with a 3D graphics, H.264 codec
engine, and a reconfigurable processor Masanobu Okabe - Sony
A Low-Power Opteron Processor Mike Leary - AMD
2:30- 2:50 Break
2:50- 4:20 Session 9: Instruction Set Automation
The End of ISA Design: Power Tools for Optimal Processor Generation
David Goodwin - Tensilica
Long Words and Wide Ports: Reinventing the Configurable Processor
Dhanendra Jani, Gulbin Ezer, James Kim - Tensilica
OptimoDEJ Krisztian Flautner - ARM
4:20- 4:50 Break
4:50- 6:20 Session 10: High-End Processors
The Montecito Processor Cameron McNairy, Rohit Bhatia - Intel
A 32-way Multithreaded SPARC Processor Poonacha Kongetira - Sun
Intel Pentium 4 Processor on 90nm Technology Ronak Singhal - Intel
6:20- 6:30 Closing Remarks
==========================
Registration for HOT Chips 16 is available through our secure web server at
http://www.hotchips.org
Payment can be made with all common credit cards. A receipt can be printed
after the registration is completed and a confirmation email will be sent to
the email address provided. Discounted early registration rates apply if
payment is completed on or before August 1, 2004. Online registration will
continue to be available until August 20, 2004 at the higher Late/Onsite
registration rate. After August 20, 2004 all registrations must be done
on-site at the conference.
Refund requests must reach us on or before August 1, and are subject to a
$25 processing fee. Students are required to show valid picture ID cards.
Please remember to bring your IEEE or ACM membership number if you are
registering on-site.
For answers to questions about registration, contact us by email at:
registration@hotchips.org
For other information, contact us by email at:
info@hotchips.org
Registration Fees
Advance (on/before 8/1) Late (after 8/1)
Tutorials Conf. Both Tutorials Conf. Both
only only only only
Member $75 $240 $315 $150 $380 $530
Non-Member $90 $325 $415 $150 $475 $620
Student $75 $ 95 $170 $ 90 $120 $210
Conference registration includes:
+ Conference Attendance
+ One copy of presentation notes
+ Monday and Tuesday luncheons
+ Coffee breaks
+ Sunday afternoon wine and cheese reception
+ Monday HOT Chips evening dinner and Panel
+ Monday and Tuesday Parking
Tutorial registration includes:
+ Attendance for both Morning and Afternoon tutorials
+ One copy of tutorial notes
+ Sunday Luncheon
+ Coffee breaks
+ Sunday afternoon wine and cheese reception
+ Sunday Parking
Location:
HOT Chips and HOT Interconnects will be held in Memorial Auditorium on the
Stanford University campus, Palo Alto, California, approximately 24 miles
from San Francisco airport and 15 miles from San Jose airport.
Directions, Maps:
>From San Francisco: take Highway 101 south.
>From San Jose: take Highway 101 north.
+ Exit 101 at Embarcadero Rd. (west) and drive 3 miles until you
enter Stanford campus on Galvez St.
+ Keep to the left on Galvez, then turn right at Campus Drive.
Parking is between Galvez and Palm Dr.
+ Walk along Galvez to the end, then turn right for Memorial
Auditorium, opposite Hoover Tower.
More details can be found on the attendee page on our website at
http://www.hotchips.org/hc16/attendee
Mass transit information is available at
http://www.transitinfo.org/
Maps of Stanford campus and surroundings are at
http://www.stanford.edu/home/visitors/maps.html
Weather:
Mid-August is typically in the 80s (F)/ 30s (C) and sunny during the day.
Nights are much cooler; a light jacket or sweater is appropriate.
Housing:
HOT Chips does not recommend any specific hotel, but refers attendees to the
following Stanford University webpage for related information:
http://www.stanford.edu/dept/hds/scs/individuals/hotelmotel.html
Reservations well in advance are advised.
On campus housing is available in student residences and can be arranged by
contacting the Stanford Summer Conference Office at
(650) 725-1429 or
summerhousing@conferences.stanford.edu or
http://www.stanford.edu/dept/hds/scs/individuals
----------------------------------------------------------------------
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* Call for Participation for ASPLOS XI
CALL FOR PARTICIPATION
Eleventh International Conference
on Architectural Support for Programming
Languages and Operating Systems
Park Plaza, Boston, Massachusetts, October 9 through 13, 2004
http://www.eecg.toronto.edu/asplos2004
The ASPLOS XI organizing committee is pleased to announce the ASPLOS XI
conference to be held in Boston, MA from Oct. 9 to Oct. 13, 2004. ASPLOS
is a multi-disciplinary conference that cultivates cross-fertilizing
research in areas of hardware, architecture, compilers, operating
systems, networking, and applications.
A preliminary program is available at the ASPLOS XI website (given
above).
The main program also includes a Wild and Crazy Ideas session. In
addition
to the main program, this year's ASPLOS offers four workshops and eight
tutorials on a variety of focus areas.
Keynote Speech:
Building Dependable Software
James R. Larus
Senior Researcher and Assistant Director
Microsoft Research
* Wild/Crazy Ideas Session
Workshops
------------------------------------------------------------------------
---
* WASSA: Workshop on Architectural Support for Security and Anti-Virus
* 1st Workshop on Building Block Engine Architectures for COmputers and
Networks
* Second Value-Prediction and Value-Based Optimization Workshop
* Operating System and Architectural Support for the on demand IT
InfraStructure
Tutorials
------------------------------------------------------------------------
* Architectures, Languages, and Compilers for the Streaming Domain
* Using the Click Modular Router for Routing, Measurement, Protocols,
and the Classroom
* Designing Instrumentation Tools With PIN
* Building Experimental Networks Using Platform FPGA's
* Using The Liberty Simulation Environment with emphasis on hardware
validated OS-level simulation
* Tutorial on Remote Direct Memory Access (RDMA) over IP transports
* Program locality models and their use in memory optimization
* Computing In The Presence of Soft Errors
----------------------------------------------------------------------
----------------------------------------------------------------------
* ISCA 2005 Call for Papers and Call for Tutorial/Workshop Proposals
ISCA 2005 Call for Papers and Call for Tutorial/Workshop Proposals
ISCA 2005 Call for Papers
32nd Annual International Symposium on Computer Architecture
Madison, Wisconsin (USA) June 4-8, 2005
http://www.cs.wisc.edu/~isca2005/
IMPORTANT DEADLINES:
Abstract Deadline: November 11, 2004
Full Paper Deadline: November 18, 2004
Workshops/Tutorials: November 24, 2004
Papers are solicited for the 32nd Annual International Symposium on
Computer Architecture. Papers are being sought on all aspects of
computer architecture, including (but not limited to):
* Processor architectures
* Memory hierarchy subsystems
* Multiprocessors and multicomputers
* Storage and interconnect subsystems
* Application-specific, reconfigurable, and embedded architectures
* Power-efficient architectures
* Dependable architectures
* Impact of technology on architecture
* Impact of application characteristics on architecture
* Architectures for emerging technologies and applications
* Performance/power evaluation and measurement of real systems
Please refer to the URL below for a complete call for papers:
http://www.cs.wisc.edu/~isca2005/
----------------------------------------------------------------------
----------------------------------------------------------------------
* Call for Papers, The Wild and Crazy Ideas Session IV
The Wild and Crazy Ideas Session IV
Held at ASPLOS XI in Boston, MA
Tuesday, October 12, 2004
In the successful tradition of the madness of past Wild and Crazy
Ideas (WACI) Sessions, ASPLOS again seeks to provide a forum for
far-out, radical, and unconventional ideas. In contrast to the papers
in the main ASPLOS program, submissions to the WACI session will be
held to a much higher standard of novelty, and a lower standard of
scientific proof. Accepted wild and crazy submissions will excel at
highlighting interesting problems and novel approaches, but may raise
more questions than they answer. They will supply fresh insights,
unveil surprising ideas, and identify hidden trends. The underlying
goal is to free presenters from the yoke of quantitative analysis,
thus making it easier explore revolutionary (as opposed to
incremental) research. Such revolutionary work should inspire the
audience, rather than recommend a concrete design or solution.
The format of the session is anticipated to be a series of 8-minute
talks, plus time for questions. Topics of submission are expected to
be consistent with the mission of ASPLOS ---pretty much anything in
architecture, but with a special emphasis on the interplay between
architecture and programming languages and operating systems. We
explicitly decline to list specific topic areas.
Again, we are looking for new ideas, insights, concepts and problem
formulations, not for definitive, polished answers to long-standing
problems. While simple "numbers" are ok, speakers will have to
convince the audience (and us) with insights that their forward-
looking idea is good.
Talks will be chosen from one-page abstracts submitted as plain text
or pdf file.
Abstracts Due: Wednesday, August 4, 6pm CDT (no extensions)
Accept/reject: Friday, August 13
Submit via email: wildandcrazy@cs.utexas.edu
For more information: www.cs.utexas.edu/users/skeckler/wild04
WACI Asylum Superintendent: Steve Keckler
skeckler@cs.utexas.edu
Wild and Crazy Henchmen: Steve Blackburn
Steve.Blackburn@anu.edu.au
Emmett Witchel
witchel@cs.utexas.edu
----------------------------------------------------------------------
----------------------------------------------------------------------
* Call for Workshop and Tutorial Proposals for HPCA-11
********************************************************
*** HPCA-11 CALL FOR WORKSHOP AND TUTORIAL PROPOSALS ***
********************************************************
11th International Symposium on High-Performance Computer Architecture
Palace Hotel; San Francisco; February 12-16, 2005
http://www.hpcaconf.org/hpca11
--------------------------------------------------------------------------------
WORKSHOP AND TUTORIAL PROPOSAL DEADLINE: AUGUST 13, 2004
SEND PROPOSALS TO JARED STARK (jared.w.stark@intel.com)
We appreciate proposals for workshops and tutorials related to computer
architecture. See previous HPCA conferences (http://www.hpcaconf.org) for
example workshops and tutorials. Please submit your proposal of no more than a
couple pages to Jared Stark (jared.w.stark@intel.com) on or before August 13,
2004.
For workshops, please include in your proposal:
* title of the workshop
* organizers and their affiliations
* sample call for papers, including the workshop's main topics
* expected duration of the workshop; i.e., 1/2 day, full day, or 2 days
* if the workshop was previously held, the number of published papers and
attendees at the last workshop
For tutorials, include:
* title of the tutorial
* organizers, presenters, and their affiliations
* abstract of the tutorial
* a list of topics to be covered and some of their related bibliography
* expected duration of the tutorial; i.e., 1/2 day, full day, or 2 days
* if the tutorial was previously held, the location (i.e., which
conference), date, and number of attendees at the last tutorial
Sponsored by the IEEE Computer Society TC on Computer Architecture
----------------------------------------------------------------------
----------------------------------------------------------------------
* JILP Call for Predictors (Branch Predictor Competition)
The Journal of Instruction-Level Parallelism
Championship Branch Prediction
website: http://www.jilp.org/cbp
***************************
*** CALL FOR PREDICTORS ***
***************************
The 1st JILP Championship Branch Prediction Competition (CBP-1)
Sponsored by: Intel MRL and IEEE TC-uARCH
in conjunction with:
MICRO-37 (http://www.microarch.org/micro37/)
--------------------------------------------------------------------------------
Championship Branch Prediction (CBP) is a branch predictor competition.
Contestants will be given a fixed storage budget to implement their best branch
prediction algorithms on a common evaluation framework distributed by the CBP
steering committee.
OBJECTIVE
---------
The goal of the Championship Branch Prediction competition is to evaluate and
compare branch prediction algorithms in a common framework. The competition's
simple and transparent evaluation process enables dissemination of results and
techniques to the larger computer design community and allows independent
verification of the competition's results. The performance and cost metrics are
selected to be as simple and quantitative as possible
Predictors must be implemented within a fixed storage budget, and will be judged
on performance. Finalists will be selected in the first round of the
competition on the basis of predictor performance on a distributed benchmark
set. In the second round of the competition a second benchmark set (not
distributed) will be used to select the champion from the finalists.
PRIZES
------
Selected finalists (including the champion) will be published in a special issue
of the Journal of Instruction-Level Parallelism (JILP). All finalists' source
code, predictor writeups, and performance results will be made publicly
available through the CBP website. The champion will receive a trophy (details
not yet determined).
SUBMISSION REQUIREMENTS
-----------------------
See http://www.jilp.org/cbp/rules.htm for additional information and
requirements. Submissions should be sent through the CBP website,
http://www.jilp.org/cbp, and must include the following:
* Abstract: which must be submitted before Friday, October 15, 2004, 9pm PST
(one week before the predictor submission deadline).
* Writeup: of the prediction algorithm including references to published work
directly relevant to the implemented algorithm.
* Performance results: a table giving performance for the distributed trace
list.
* Branch predictor code: the driver code containing the predictor.
To prevent minor variations of a predictor, no person may be part of more than
one submission. The final submission must be submitted in its entirety before
Friday October 22, 2004, 9pm PST. No extensions will be granted. Submission
issues should be directed to the steering committee at cbp@lists.ncsu.edu.
IMPORTANT DATES
---------------
Competition formally announced at ISCA: June 19, 2004
Evaluation framework available: July 29, 2004
Abstract submission: October 15, 2004, (9pm Pacific Time, USA)
Predictor submission: October 22, 2004, (9pm Pacific Time, USA)
Finalists selected/notified: November 5, 2004
Champion selected from finalists at MICRO: December 5, 2004 (TENTATIVE)
STEERING COMMITTEE
------------------
Dan Connors Univ. of Colorado
Tom Conte North Carolina State Univ.
Konrad Lai Intel MRL
Yale Patt Univ. of Texas at Austin
Jim Smith Univ. of Wisconsin
Jared Stark Intel MRL
Mateo Valero Univ. Politecnica Catalunya
Chris Wilkerson Intel MRL
SELECTION COMMITTEE
-------------------
Dan Connors Univ. of Colorado
Tom Conte North Carolina State Univ.
Phil Emma IBM Research
Konrad Lai Intel MRL
Scott McFarling Microsoft
Chuck Moore AMD
Yale Patt Univ. of Texas at Austin
Jim Smith Univ. of Wisconsin
Jared Stark Intel MRL
Mateo Valero Univ. Politecnica Catalunya
Chris Wilkerson Intel MRL
----------------------------------------------------------------------
----------------------------------------------------------------------
* Second Value-Prediction and Value-Based Optimization Workshop Call for Papers
Call for Papers
Second Value-Prediction and Value-Based Optimization Workshop
http://www.csl.cornell.edu/VPW2/
to be held in conjunction with the
Eleventh International Conference on
Architectural Support for Programming Languages and Operating Systems
Boston, Massachusetts
October 9 or 10, 2004
Theme
The Second Value-Prediction and Value-Based Optimization Workshop
(VPW2) encompasses all hardware and software speculation mechanisms
that make or use multi-bit predictions as well as value profiling and
other value-based optimization techniques.
Extended versions of selected papers will be invited for publication
in the Journal of Instruction-Level Parallelism.
Topics
- value predictors
- confidence estimators
- value profiling
- value-based compiler optimizations
- value-based power reduction
- misprediction recovery schemes
- latency predictors
- dependency predictors
- coherency predictors
- address predictors (prefetchers)
- branch target predictors
- etc.
Important Dates
- Submission: July 29 (5pm EDT)
- Notification: September 2
- Final papers: September 23
Submission Guidelines
Submissions must use ten-point or larger fonts, one-inch margins,
US letter size format, and are not to exceed six pages (including
everything). Papers should be submitted in PDF with all fonts
embedded. Please email submissions and questions to
vpw2@csl.cornell.edu.
Organizers
- Martin Burtscher (Cornell University)
- Amer Diwan (University of Colorado at Boulder)
Program Committee
- Martin Burtscher (Cornell University)
- Amer Diwan (University of Colorado at Boulder)
- Lizy K. John (The University of Texas at Austin)
- David R. Kaeli (Northeastern University)
- Gabriel H. Loh (Intel / Georgia Institute of Technology)
- Mary Lou Soffa (University of Pittsburgh)
- Dean M. Tullsen (University of California, San Diego)
- Benjamin G. Zorn (Microsoft)
----------------------------------------------------------------------
----------------------------------------------------------------------
* Workshop on Workload Characterization Call for Papers
http://www.ece.utexas.edu/~ljohn/wwc/
Submitted by Tao Li <taoli@ece.ufl.edu>
----------------------------------------------------------------------
----------------------------------------------------------------------
* 2004 OASIS Workshop - Call for Papers
********************************************
* 2004 OASIS Workshop - Call for Papers *
********************************************
1st Workshop on Operating System and Architectural Support
for the on demand IT InfraStructure
http://www.research.ibm.com/actc/OASIS-2004/
Oct 9, 2004
Held along with ASPLOS-XI
Park Plaza, Boston, Massachusetts
Oct 9-13, 2004
Overview of the Workshop:
The demand on today's IT infrastructures is rapidly changing. Fueled by
an ever-increasing data-centric society that desires information anywhere,
anytime and anyhow, workloads have shifted from predominantly backdoor
batch processing and static information serving to dynamic transactions
and web services. Such changed workloads are often difficult to predict
and hence require flexibility in the IT itself to be able to react on
demand and improve operation. With the increased flexibility arises a
new level of complexity that needs to be addressed. Furthermore,
adequate support for this data-centric world is requiring the system
infrastructure to provide high level of resilience and differentiated
levels of robustness and availability for various kinds of IT services.
This workshop focuses on operating system and architecture support to
facility such on demand infrastructures.
The OASIS-1 workshop will be held along with ASPLOS XI and is intended
to bring together researchers from academia and industry for an engaging
discussion on architecture and operating system support in the emerging
field of on demand infrastructures.
Topics of Interest (not limited to):
* Hardware and Operating System Support for Server Virtualization.
* Flexible Storage / Network integration with Server
* Application Management
* Flexible techniques for Security and robustness of on-demand systems
* Resource management for on-demand computing
* Operating system support for scalable computing services
* Application experiences with deployed on-demand IT infrastructures
Paper Submission Information:
We welcome submissions in the form of short papers (6 double-column pages)
or extended abstracts (5 pages).
Please e-mail your submissions (preferably in pdf) to frankeh@us.ibm.com
and nieh@cs.columbia.edu . Submissions are due by August 7th.
Workshop Chairs:
Hubertus Franke IBM Research frankeh@us.ibm.com
Jason Nieh Columbia University nieh@cs.columbia.edu
Organizing / Program Committee:
Andrew Chien UC San Diego
Graeme Dixon IBM Research
Joefon Jann IBM Research
Scott Kaplan Amherst College
Angelos Keromytis Columbia University
Beng-Hong Lim VMware
Shailabh Nagar IBM Research
Klaus Schauser Citrix
Karsten Schwan Georgia Tech
Uwe Schwiegelshohn University of Dortmund
Important Dates:
Paper Submission August 7, 2004
Author Notification September 1, 2004
Final Paper Submission September 14, 2004
For More Information:
Please send mail to frankeh@us.ibm.com or nieh@cs.columbia.edu
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* Call for Participation - SCOPES 2004 Amsterdam, The Netherlands
ON-LINE REGISTRATION IS OPEN FOR SCOPES 2004
http://www.scopes2004.org/registration.html
!!!!!!!!!!!!!REGISTER NOW!!!!!!!!!!!!!!!!!
Deadline for early registration: August 1st, 2004
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SCOPES is the workshop for researchers, developers,
educators and practitioners to exchange their
knowledge on software for embedded systems.
SCOPES will be held in Amsterdam, The Netherlands, on
September 2nd and 3rd, 2004.
This year's SCOPES workshop features:
- Keynote address by Mike Uhler (CTO, MIPS):
- The new economics of embedded systems
- 17 presentations (selected from around 50 excellent
submissions) on:
- Application specific (co)design
- System & application synthesis
- Data flow analysis
- Data partioning
- Task scheduling
- Code generation
- 2 Panel sessions on:
- Future of Embedded Systems Programming
- Academia and Industry, Bridging the Gap
- Best paper award
- 2 Social events
The proceedings will be published by Springer in the
Lecture Notes in Computer Science (LNCS) series
ALL RECENT INFO AND ON-LINE REGISTRATION
can be found at:
http://www.scopes2004.org
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* New papers published online by Computer Architecture Letters
Computer Architecture Letters announces our most recent paper, which is
publicly available at
http://www.comp-arch-letters.org/2004paps.html. We continue to seek new
submissions and remain committed to fast and accurate review. Our mean
time to decision remains one month, with an acceptance rate of
approximately 21%. For more information on submission, please see
http://www.comp-arch-letters.org
M. E. Gomez, J. Duato, J. Flich, P. Lopez, A. Robles, N. A. Nordbotten,
O. Lysne, T. Skeie. "An Efficient Fault-Tolerant Routing Methodology for
Meshes and Tori." Volume 3, May. 2004.
Abstract:
In this paper we present a methodology to design fault-tolerant routing
algorithms for regular direct interconnection networks. It supports
fully adaptive routing, does not degrade performance in the absence of
faults, and supports a reasonably large number of faults without
significantly degrading performance. The methodology is mainly based on
the selection of an intermediate node (if needed) for each
source-destination pair. Packets are adaptively routed to the
intermediate node and, at this node, without being ejected, they are
adaptively forwarded to their destinations. In order to allow
deadlock-free minimal adaptive routing, the methodology requires only
one additional virtual channel (for a total of three), even for tori.
Evaluation results for a 4x4x4 torus network show that the methodology
is 5-fault tolerant. Indeed, for up to 14 link failures, the percentage
of fault combinations supported is higher than 99.96%. Additionally,
network throughput degrades by less than 10% when injecting three random
link faults without disabling any node. In contrast, a mechanism similar
to the one proposed in the BlueGene/L, that disables some network
planes, would strongly degrade network throughput by 79%.
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