Mailing List Archives
Mail Index
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
SIGARCH-MSG: May 2004 Digest of SIGARCH Messages
This is the May 2004 Digest of SIGARCH Messages (sigarch-may04):
* SCOPES 2004 Call for Papers
http://www.scopes2004.org
Submitted by Henk Schepers <henk.schepers@philips.com>
* HPCA-11 Call for Papers
http://www.hpcaconf.org/hpca11
Submitted by Christos Kozyrakis <christos@ee.stanford.edu>
* MICRO-37 Call for Papers
http://www.microarch.org/micro37
Submitted by Glenn Reinman <reinman@CS.UCLA.EDU>
* Computer Architecture Letters publishes new paper
http://www.comp-arch-letters.org/2004paps.html
Submitted by Kevin Skadron <skadron@cs.virginia.edu>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org
* Archive: http://www.cs.wisc.edu/~lists/archive/sigarch-members/maillist.html
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail listserv@acm.org with message body: unsubscribe SIGARCH-MEMBERS
-----------------------------------------------------------------
Doug Burger Office: 3.432 ACES
Assistant Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
The University of Texas at Austin Fax: 512-232-1413
1 University Station, #C0500 E-mail: dburger@cs.utexas.edu
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
-----------------------------------------------------------------
* SCOPES 2004 Call for Papers
http://www.scopes2004.org
Submitted by Henk Schepers <henk.schepers@philips.com>
**********************************************************************
SCOPES 2004
8th International Workshop on Software and
Compilers for Embedded Systems
September 2 - 3, 2004
NH Amsterdam Centre hotel, Amsterdam
http://www.scopes2004.org
**********************************************************************
The scope of the workshop is software for embedded systems. The
emphasis is on code generation techniques (compilers) for embedded
processors which consider their typical characteristics, for instance
heterogeneous register files, VLIW parallelism and special architectural
features for signal processing or microcontroller applications.
Topics of highest interest include:
- code generation for embedded processors
- compilers for reconfigurable architectures
- retargetable compilation techniques for fast design space exploration
- compilation for hardware/software co-design
- application specific programmable core/software development tools
co-design
- profiling and analysis techniques for embedded software
- optimizations for embedded Java
- specification and validation techniques for embedded software
- run-time support and real-time operating systems
- software synthesis
- exploitation of memory hierarchies
- optimization for low-power architectures
- design of embedded software
SCOPES 2004 solicits in particular papers on compilation and software
design for heterogeneous single chip multi-core processors, including
the partitioning and debugging of the software for such processors.
The plan is to have one day of the workshop devoted to compilers for
embedded processors and one day on general issues related to embedded
software and embedded processor architectures. In addition, there will
be a keynote presentation by a well-known speaker.
A key goal of the workshop is to provide an interactive atmosphere.
Questions are welcomed during all presentations. There will be sessions
to discuss specific topics. The workshop is open to all interested
participants active in the field.
Submitting Papers
Papers should present original, new research results not published
or submitted for publication in other forums. Papers should not exceed
15 pages (LNCS format) in postscript, PDF or RTF format. Papers should
be submitted using the submission page, which will be opened on
March 15th.
Important Dates
Abstracts due: April 8th, 2004. Strict paper submission deadline:
April 15th, 2004. Notification of acceptance: May 24th. The deadline
for the camera-ready final version is June 21st, 2004.
General chairs
- Marco Roodzant, ACE Associated Compiler Experts
- Henk Schepers, Philips Research
Local organisation
- Marianne Dalmolen, ACE Associated Compiler Experts
Program Committee
- Uwe Assmann, Linköpings Universitet
- Lex Augusteijn, Silicon Hive
- Shuvra Bhattacharyya, University of Maryland
- Albert Cohen, INRIA
- Alex Dean, North Carolina State University
- Nikil Dutt, University of California at Irvine
- Antonio González, Universitat Politècnica de Catalunya & Intel Labs
- David Gregg, Trinity College Dublin
- Rajiv Gupta, University of Arizona
- Seongsoo Hong, Seoul National University
- Nigel Horspool, Victoria University
- Masaharu Imai, Osaka University
- Ahmed Jerraya, IMAG
- Daniel Kästner, AbsInt
- Andreas Krall, Technische Universität Wien
- Rainer Leupers, RWTH Aachen
- Annie Liu, SUNY Stony Brook
- Peter Marwedel, Universität Dortmund
- Tatsuo Nakajima, Waseda University
- Alex Nicolau, University of California at Irvine
- Yunheung Paek, Seoul National University
- Santosh Pande, Georgia Institute of Technology
- Robert Pasko, IMEC
- Sreeranga Rajan, Fujitsu
- Miguel Santana, STMicroelectronics
- Hans van Someren, ACE Associated Compiler Experts
- Hiroyuki Tomiyama, Nagoya University
- Bernard Wess, Technische Universität Wien
- David Whalley, Florida State University
**************************************************************************
----------------------------------------------------------------------
----------------------------------------------------------------------
* HPCA-11 Call for Papers
http://www.hpcaconf.org/hpca11
Submitted by Christos Kozyrakis <christos@ee.stanford.edu>
HPCA-11 Call for Papers
11th International Symposium on High-Performance Computer Architecture
Palace Hotel, San Francisco, February 12-16, 2005
http://www.hpcaconf.org/hpca11
The International Symposium on High-Performance Computer Architecture
provides a high-quality forum for scientists and engineers to present
their latest research findings in this rapidly-changing field. Authors
are invited to submit papers on all aspects of high-performance
computer architecture. Topics of interest include, but are not limited
to:
* Processor architectures
* Cache and memory systems
* Parallel computer architectures
* Impact of technology on architecture
* Power-efficient architectures and techniques
* High-availability architectures
* High-performance I/O systems
* Embedded and reconfigurable architectures
* Interconnect and network interface architectures
* Network processor architectures
* Innovative hardware/software trade-offs
* Impact of compilers on architecture
* Performance evaluation of real machines
Authors should submit an abstract before Monday, July 12, 2004, 9pm
PST. They should submit the full version of the paper before Monday,
July 19, 2004, 9pm PST. No extensions will be granted. The full
version should be a PDF file that does not exceed 6,000 words
according to the instructions in http://www.hpcaconf.org/hpca11.
Papers that exceed the length limit or that cannot be viewed using
Adobe Acrobat Reader (version 3.0 or higher) may not be
reviewed. Papers should be submitted for blind review. Please indicate
whether the paper is a student paper for best student paper
nominations.
Papers will be evaluated based on their novelty, fundamental insights,
and potential for long-term contribution. New-idea papers are
encouraged.
Submission issues should be directed to the program chair at
torrellas@cs.uiuc.edu. Workshop and tutorial submissions should be
directed to the workshop and tutorial chair at
jared.w.stark@intel.com.
Important dates
* Abstract submission: July 12, 2004, 9pm PST (firm deadline)
* Paper submission: July 19, 2004, 9pm PST (firm deadline)
* Workshop and tutorial proposals due: August 13, 2004
* Notification of paper outcome: September 25, 2004
Sponsored by the IEEE Computer Society TC on Computer Architecture.
General Chair
Justin Rattner, Intel
Program Chair
Josep Torrellas, Univ. of Illinois
Program Committee
Sarita Adve, Univ. of Illinois
David Albonesi, Univ. of Rochester
Krste Asanovic, MIT
Ricardo Bianchini, Rutgers Univ.
Angelos Bilas, Univ. of Crete
Pradip Bose, IBM
Brad Calder, Univ. of California, San Diego
John Carter, Univ. of Utah
Alok Choudhary, Northwestern Univ.
Tom Conte, North Carolina State Univ.
Jose Duato, Univ. Politecnica Valencia
Michel Dubois, Univ. of Southern California
Kemal Ebcioglu, IBM
Kourosh Gharachorloo, Google
Antonio Gonzalez, Univ. Politecnica Catalunya
Rajiv Gupta, Univ. of Arizona
Michael Huang, Univ. of Rochester
Mary Jane Irwin, Pennsylvania State Univ.
Lizy John, Univ. of Texas
David Kaeli, Northeastern Univ.
Steve Keckler, Univ. of Texas
Diana Marculescu, Carnegie Mellon Univ.
Shubu Mukherjee, Intel
Mark Oskin, Univ. of Washington
Timothy Pinkston, Univ. of Southern California
Steve Scott, Cray
Andre Seznec, IRISA/INRIA
John Shen, Intel
Anand Sivasubramaniam, Penn. State Univ.
Kevin Skadron, Univ. of Virginia
Yan Solihin, North Carolina State Univ.
James Smith, Univ. of Wisconsin
Mateo Valero, Univ. Politecnica Catalunya
T. N. Vijaykumar, Purdue Univ.
Yuanyuan Zhou, Univ. of Illinois
Industry Liaison Chairs
Konrad Lai, Intel
Sanjay Patel, Univ. of Illinois
Local Arrangements Chair
Murali Annavaram, Intel
Workshop and Tutorial Chair
Jared Stark, Intel
Publicity and Publications Chair
Christos Kozyrakis, Stanford Univ.
Finance and Registration Chair
Pradeep Dubey, Intel
Web Chair
Wei Liu, Univ. of Illinois
Steering Committee
Dharma Agrawal, Univ. of Cincinnati
Laxmi Bhuyan, Univ. of California, Riverside
Jose Duato, Univ. Politecnica Valencia
Jean-Luc Gaudiot, Univ. of California, Irvine
Yale Patt, Univ. of Texas
Francisco Tirado, Univ. Complutense Madrid
Emilio L. Zapata, Univ. of Malaga, Spain
----------------------------------------------------------------------
----------------------------------------------------------------------
* MICRO-37 Call for Papers
http://www.microarch.org/micro37
Submitted by Glenn Reinman <reinman@CS.UCLA.EDU>
---------------------------------------------------------------------
MICRO-37 Call for Papers
THE 37th ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE
Portland, OR, December 6-8th, 2004
http://www.microarch.org/micro37
---------------------------------------------------------------------
Abstract & Full Paper Submission Deadline: May 28th, 2004
Papers are solicited for the 37th Annual International Symposium on
Microarchitecture. Papers are being sought on all aspects of computer
architecture, including (but not limited to) the following:
* Microarchitecture and compilation techniques for
instruction-level, thread-level, and memory-level parallelism
* Speculation on control flow, data flow, and synchronization
* Hardware/software based runtime/link-time optimizations
* Translation, emulation, and optimization of object code
* Workload analysis and phase detection for microarchitectures
* Multi-thread, multi-cluster, multi-core processors and systems
* Application-specific processors and integrated coprocessors
* Processors for media, data-mining, and packet processing
* Power, performance and implementation efficient designs
* Memory system optimizations: latency, bandwidth, prefetching
* Microarchitecture modeling and simulation methodology
* Measurement and analysis of real microarchitectures
* Microarchitecture support for dependability and security
There is an automatic 1-week extension (June 4th, 2004) for submitting
the full paper, but no extension on abstract submission. Please
submit, using our website, one electronic copy of the paper in PDF
format, not to exceed 22 double-spaced single-column pages and 5000
words. Author notification will be August 16th, 2004.
The 37th International Symposium on Microarchitecture will be held at
the Doubletree Hotel in Portland, Oregon. MICRO is the premier forum
for presenting, discussing and debating new and innovative
microarchitecture ideas and techniques for advanced computing and
communication systems. The goal of this symposium is to bring together
researchers in fields related to processor architecture, compilers,
and systems, for technical exchange on traditional MICRO topics as
well as new emerging research areas. Historically, the MICRO community
has enjoyed having close interaction between academic researchers and
industrial designers; we aim to continue and emphasize this tradition
at MICRO-37.
Please refer to http://www.microarch.org/micro37 for the complete call
for papers and other details about the symposium.
----------------------------------------------------------------------
----------------------------------------------------------------------
* Computer Architecture Letters publishes new paper
Computer Architecture Letters announces our most recent paper, which is
publicly available at
http://www.comp-arch-letters.org/2004paps.html. We continue to seek new
submissions and remain committed to fast and accurate review. Our mean
time to decision remains one month, with an acceptance rate of
approximately 21%. For more information on submission, please see
http://www.comp-arch-letters.org
A. Singh, W. J. Dally, B. Towles, A. K. Gupta. "Globally Adaptive
Load-Balanced Routing on Tori." Volume 3, Mar. 2004.
Abstract:
We introduce a new method of adaptive routing
on k-ary n-cubes, Globally Adaptive Load-Balance (GAL). GAL
makes global routing decisions using global information. In
contrast, most previous adaptive routing algorithms make local
routing decisions using local information (typically channel queue
depth). GAL senses global congestion using segmented injection
queues to decide the directions to route in each dimension. It
further load balances the network by routing in the selected
directions adaptively. Using global information, GAL achieves
the performance (latency and throughput) of minimal adaptive
routing on benign traffic patterns and performs as well as the
best obliviously load-balanced routing algorithm (GOAL) on
adversarial traffic.
[Other mailing list archives]
[CS Dept. Home Page]