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SIGARCH-MSG: November 2003 Digest of SIGARCH Messages
This is the November 2003 Digest of SIGARCH Messages (sigarch-nov03):
* SIGMETRICS 2004 Call for Papers
http://www.cs.columbia.edu/~sigm2004/
Submitted by Jason Nieh <nieh@cs.columbia.edu>
* ASPLOS-XI Call for Papers
http://www.eecg.toronto.edu/asplos2004
Submitted by Shubu Mukherjee <shubu.mukherjee@intel.com>
* 10th International Symposium on High-Performance Computer Architecture Call for Participation
http://www.ac.uma.es/hpca10/
Submitted by Jose F. Martinez <martinez@csl.cornell.edu>
* ODES: 2nd Workshop on Optimizations for DSP and Embedded Systems
http://www.ece.vill.edu/~deepu/odes/odes.html
Submitted by Deepu Talla <deepu@ti.com>
* New papers published online by Computer Architecture Letters
http://www.comp-arch-letters.org/2003paps.html
Submitted by Kevin Skadron <skadron@cs.virginia.edu>
* HotLeakage v1.0 release
http://lava.cs.virginia.edu/HotLeakage
Submitted by Kevin Skadron <skadron@cs.virginia.edu>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org
* Archive: http://www.cs.wisc.edu/~lists/archive/sigarch-members/maillist.html
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail listserv@acm.org with message body: unsubscribe SIGARCH-MEMBERS
-----------------------------------------------------------------
Doug Burger Office: 3.432 ACES
Assistant Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
University of Texas at Austin Fax: 512-232-1413
Taylor Hall 2.124 E-mail: dburger@cs.utexas.edu
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* SIGMETRICS 2004 Call for Papers
******SIGMETRICS 2004/ Performance 2004 ******
Joint International Conference on
Measurement and Modeling of Computer Systems
Sponsored by ACM SIGMETRICS and IFIP Working Group 7.3
June 12-16th, 2004, New York, NY
http://www.cs.columbia.edu/~sigm2004/
The joint SIGMETRICS/Performance conference solicits papers on the
development and application of state-of-the-art, broadly applicable
analytic, simulation, and measurement-based performance evaluation
techniques. Of particular interest is work that furthers the
state-of-the-art in performance evaluation methods, or combines
analytic and experimental methods to evaluate design trade-offs in real
systems.
Topics of interest include but are not limited to:
- Performance-oriented design and evaluation studies of communication
networks, Internet servers, computer architectures, database
systems, operating systems, distributed systems, multimedia systems,
mobile and handheld systems, file and I/O systems, memory systems,
real-time systems, and dependable systems, including case studies
and performance-evaluation tools.
- Performance methodology techniques, algorithms, and tools for
analytic modeling, system measurement and monitoring, model
verification and validation, workload characterization, simulation,
statistical analysis, stochastic modeling including queues,
stochastic Petri nets, stochastic process algebras, model checking,
experimental design, reliability and availability analysis, power
analysis, performance optimizations, and hybrid models.
Submission Guidelines
=====================
- Papers: Papers must not exceed 12 pages, using 9-point or larger
fonts, in double-column format. Detailed submission guidelines are
available at the conference web site.
- Hot Topic Sessions: Proposals are solicited for a hot topic session,
in which a group of speakers will present and discuss their recent
results in an area. Send proposals to the program chairs,
identifying the organizer of the session, the session title, three
to five speakers, the titles of their talks, and a short abstract of
each talk.
- Tutorials: A series of tutorials will immediately precede the main
conference. Send proposals of no more than 1 or 2 pages (for
90-minute or 3-hour tutorials) to the tutorials chair. Include the
proposed title, brief description of material, intended audience,
assumed background of attendees, and the name, affiliation, contact
information (e-mail and phone), and brief biography of speaker(s).
Postscript or PDF is preferred.
Important Dates:
================
November 2, 2003: Paper title, abstract, and author affiliations due.
November 7, 2003: Full papers, tutorials, and hot topic proposals due
(HARD deadline, no extensions)
January 29, 2004: Notification of acceptance
For more and up to date information see the conference web site
at: http://www.cs.columbia.edu/~sigm2004/.
Organization
============
General Chair:
E. G. Coffman, Jr. (Columbia University) egc@ee.columbia.edu
Program Co-Chairs:
Zhen Liu (IBM Research) zhenl@us.ibm.com
Arif Merchant (HP Labs) arif@hpl.hp.com
Local Arrangement Chair:
Vishal Misra (Columbia University) misra@cs.columbia.edu
Tutorials Chair:
Li Zhang (IBM Research) zhangli@us.ibm.com
Proceedings Chair:
Yefim Shuf (IBM Research) yefim@us.ibm.com
Publicity Chair:
Jason Nieh (Columbia University) nieh@cs.columbia.edu
Finance Chair:
Sambit Sahu (IBM Research) sambits@us.ibm.com
Web Masters:
Angelos Stavrou (Columbia University) angelos@ee.columbia.edu
Hanhua Feng (Columbia University) hanhua@cs.columbia.edu
Program Committee:
Ajmone-Marsan, Marco Politecnico di Torino, Italy
Baccelli, Francois ENS, France
Barford, Paul U. Wisconsin, USA
Bershad, Brian U. Washington, USA
Biersack, Ernst Eurecom, France
Bonald, Thomas France Telecom, France
Borst, Sem CWI, Netherlands
Cao, Pei Cisco, USA
Chang, Cheng-Shang National Tsing Hua Univ. Taiwan
Chase, Jeff Duke University, USA
Cherkasova, Lucy HP Labs, USA
de Souza e Silva, Edmundo UFRJ, Brazil
Douceur, John Microsoft Research, USA
Duffield, Nick AT&T Research, USA
Eager, Derek U Saskatchewan, Canada
Golubchik, Leana USC, USA
Harchol-Balter, Mor Carnegie Mellon University, USA
Jean-Marie, Alain Uni Montpellier, France
Keeton, Kimberly HP Labs, USA
Kumar, Anurag IISc, India
Kurose, Jim Univ. Massachusetts, USA
LeBoudec, Jean-Yves EPFL, Switzerland
Long, Darrell UCSC, USA
Lui, John Chinese U. of Hong Kong, China
Mazumdar, Ravi Purdue University, USA
Misra, Vishal Columbia University, USA
Mitra, Debasis Bell Laboratories, USA
Muntz, R.Richard UCLA, USA
Nahum, Erich IBM Research, USA
Nain, Philippe INRIA, France
Nieh, Jason Columbia University, USA
Ross, Keith Brooklyn Poly University, USA
Sanders, William UIUC, USA
Setia, Sanjeev George Mason Univ., USA
Shenoy, Prashant Univ. Massachusetts, USA
Smirni, Evgenia College of William & Mary, USA
Squillante, Mark IBM Research, USA
Srikant, Rayadurgam UIUC, USA
Towsley, Don Univ. Massachusetts, USA
Tripathi, Satish UC at Riverside, USA
Verscheure, Olivier IBM Research, USA
Vernon, Mary U Wisconsin-Madison, USA
Williamson, Carey University of Calgary, Canada
Woodside, Murray C. Carleton University, Canada
Xia, Cathy IBM Research, USA
Yao, David Columbia University, USA
Zhang, Zhi-Li U Minnesota, USA
----------------------------------------------------------------------
----------------------------------------------------------------------
* ASPLOS-XI Call for Papers
Eleventh International Conference on
Architectural Support for Programming Languages and Operating Systems
Park Plaza, Boston, Massachusetts, October 9 though 13, 2004
------------------------------------------------------------------------------
IMPORTANT DEADLINES
Abstract Deadline: Friday, Feb. 27, 2004 (*)
Full Paper Deadline: Friday, March 5, 2004 (*)
Tutorials Submission Deadline: Friday, April 16, 2004
Notification of Acceptance: Saturday, May 22, 2004
Tutorial Notification: Friday, June 4, 2004
Final Paper Submission: Tuesday, July 20, 2004
(*) Deadlines are firm at 18:00 PST.
SCOPE
ASPLOS is a multi-disciplinary conference that seeks cross-fertilizing
research in areas of hardware, architecture, compilers, operating
systems, networking, and applications. It has captured some of the
major computer systems innovations of the past 15 years (e.g., RISC and
VLIW processors, small and large-scale multiprocessors, clusters and
networks-of-workstations, optimizing compilers, RAID, and network-storage
system designs). Today multi-disciplinary research is becoming even more
important, as boundaries between hardware/software and local/network computing
blur, as the form and capabilities of computing devices becomes ever more
varied, and as the user-base and applications expand exponentially. Like its
predecessors, the eleventh ASPLOS conference will focus on ground-breaking
multi-disciplinary research. In addition, the program committee welcomes
research papers on a wide range of non-traditional topics that emphasize
the multi-disciplinary aspects of their work. As ASPLOS expands its scope,
we encourage questions to the Program Chair regarding suitability of a topic.
Full papers are solicited on, but not limited to, these topics:
+ Interaction of operating systems, compilers, programming languages,
and architectures
+ Hardware/software issues for new devices, from sensor networks to
wireless PDAs to wall-sized displays
+ Hardware/software issues for embedded systems
+ Hardware/software platform issues focusing on Internet services
+ Hardware/software platforms for delivering graphics and multimedia
+ Embedding computation and storage (e.g., caches) within the network
+ Case studies of hardware/software design in novel experimental
systems
+ Studies of Internet applications and services with implications
for systems
+ Performance evaluation of experimental systems
+ Effect of future VLSI technology and emerging applications on
architectures, operating systems, or compilers
The program committee and designated reviewers will read all submissions,
and will evaluate them based on scientific merit, innovation, relevance,
and presentation. ``New-idea'' papers are encouraged; the program committee
recognizes that such papers may contain a significantly less thorough
evaluation than papers in more established areas. The committee will
also give special consideration to controversial papers that stimulate
interesting debate during the committee meeting. Accepted papers will
be published in a conference proceedings that will be distributed at the
conference and published as an issue of the ACM SIGARCH, SIGOPS and SIGPLAN
newsletters. Submitted papers must not be simultaneously under review for
any other conference or journal, and authors should point out any substantial
overlap with their previously published or currently submitted work.
Please check the following web site for up-to-date information:
http://www.eecg.toronto.edu/asplos2004
-------------------------------------------------------------------------------
GENERAL CHAIR
Shubu Mukherjee, Intel
PROGRAM CHAIR
Kathryn S. McKinley, Univ. of Texas
STEERING COMMITTEE
Alan Berenbaum, Agere Systems
Joel Emer, Intel
Evelyn Duesterwald, IBM
Kourosh Gharachorloo, Google
Larry Peterson, Princeton Univ.
Larry Rudolph, MIT
David Wood, Univ. of Wisconsin-Madison
PROGRAM COMMITTEE
Anant Agarwal, MIT
Todd Austin, Univ. of Michigan
Hari Balakrishnan, MIT
Stephen M. Blackburn, Australian National Univ.
Doug Burger, Univ. of Texas at Austin
Brad Calder, Univ. of California, San Diego
John Carter, Univ. of Utah
Elmootazbellah Elnozahy, IBM Austin Research
Greg Ganger, Carnegie Mellon Univ.
Monica Lam, Stanford Univ.
Hank Levy, Univerisity of Washington, Seattle
Margaret Martonosi, Princeton Univ.
Todd Mowry, Carnegie Mellon Univ.
Shubu Mukherjee, Intel
Mary Lou Soffa, Univ. of Pittsburgh
Gurindar S. Sohi, Univ. of Wisconsin-Madison
Olivier Temam, Université Paris Sud
Chandu Thekkath, Microsoft Research
WORKSHOPS/TUTORIALS CHAIR
Dirk Grunwald, Univ. of Colorado at Boulder
FINANCE CHAIR
Steve Reinhardt, Univ. of Michigan
REGISTRATION CHAIR
Dave Kaeli, Northeastern Univ.
LOCAL ARRANGEMENTS
Nancy Cross, HP
PUBLICATIONS CHAIR
Mithuna Thottethodi, Purdue Univ.
WILD/CRAZY IDEAS SESSION CHAIR
Steve Keckler, Univ. of Texas
BANQUET ARRANGEMENTS
Lisa Wu, Intel
PUBLICITY CHAIR
Andreas Moshovos, Univ. of Toronto
------------------------------------------------------------------------------
ASPLOS-XI Call for Tutorial/Workshop Proposals
Eleventh International Conference on
Architectural Support for Programming Languages and Operating Systems
Park Plaza, Boston, Massachusetts, October 9 though 13, 2004
------------------------------------------------------------------------------
Several workshops and tutorials are planned to be offered in conjunction
with ASPLOS-XI, immediately before the conference proper. Organizers are
invited to submit proposals on all aspects of high-performance computer
architecture and its interaction with operating systems and programming
languages to the Workshops Chair Dirk Grunwald (grunwald@cs.colorado.edu)
by April 16. Topics of interest include, but are not limited to, the
ones listed in the Call for Papers.
----------------------------------------------------------------------
----------------------------------------------------------------------
* 10th International Symposium on High-Performance Computer Architecture Call for Participation
Call for Participation
HPCA-10
10th International Symposium on High-Performance Computer Architecture
Madrid, Spain
February 14-18, 2004
http://www.ac.uma.es/hpca10/
The International Symposium on High-Performance Computer Architecture
provides a high quality forum for scientists and engineers to present
their latest research findings in this rapidly changing field.
Final program and information on tutorials can be found at:
http://www.ac.uma.es/hpca10/program.html
Information on workshops and tutorials is available at:
http://www.csl.cornell.edu/~espeight/hpca10wkshps.html
http://www.ac.uma.es/hpca10/tutorials.html
Registration is now open. Early registration period ends Jan. 16, 2004.
On-site registration may be required after Feb. 6, 2004. Please register
following instructions at:
http://www.ac.uma.es/hpca10/registration.html
Hotel rooms are available at special rates for HPCA-10 conference attendees
in Madrid at several locations. Convenient transportation is available from
any of them to the conference site (UCM campus). For more details,
please see:
http://www.ac.uma.es/hpca10/hotel.html
HPCA-10 conference and workshops will be held at Facultad de Informatica
of the Universidad Complutense, in Madrid. For transportation details,
please refer to:
http://www.ac.uma.es/hpca10/travel.html
Finally, to find out what you can see and do in Madrid, please visit:
http://www.ac.uma.es/hpca10/madrid.html
See you in Madrid!
----------------------------------------------------------------------
----------------------------------------------------------------------
* ODES: 2nd Workshop on Optimizations for DSP and Embedded Systems
http://www.ece.vill.edu/~deepu/odes/odes.html
March 21, 2004
--------------
Hayes Mansion and Conference Center, San Jose, California
in conjunction with IEEE/ACM International Symposium on
Code Generation and Optimization (CGO)
http://www.cgo.org
CALL FOR PAPERS
===============
The performance requirements of digital signal processing and
embedded applications are rapidly increasing, but the power and
cost budgets are decreasing. Optimization plays a very important role
in managing the conflicting demands. The focus of this workshop is to
understand the various optimization strategies applicable to the design
of DSP and embedded systems for performance, power, and cost.
Topics of Interest
------------------
Topics of interest include, but are not limited to:
+ Algorithmic transformations and code/software optimization
+ Hardware and software optimizations for low-power consumption and
code density
+ Coprocessor and hardware accelerators
+ Compiler techniques and code generation for media processing
+ Frameworks for profiling and scheduling tasks (multiple/concurrent) on
various hardware resources (single-core + hardware accelerators,
dual-core, system-on-a-chip, etc)
+ Hardware/software tradeoffs with ASICs, FPGA's, DSPs, general-purpose
processors, microcontrollers, etc as building blocks
+ Retargetable compilers and reconfigurable architectures
Important dates and deadlines
-----------------------------
+ Submission: January 9, 2004
+ Acceptance: February 13, 2004
+ Final version: March 5, 2003
Submission guidelines
---------------------
To encourage participation, we are not asking for full papers for this
workshop. Please submit an extended abstract, and a corresponding foil
set. The final digest of the workshop will consist of presentation slides
only. The purpose of the extended abstract is to augment the reviewers
ability to judge the submission. There is no limit on the length of the
extended abstract (can be anywhere from 2-3 pages to a full paper if the
author chooses so). By only publishing the slides, we allow the authors
to submit incremental work (to their accepted ODES submission) to a full
fledged conference without significant duplication concerns. Clearly
describe the nature of the work, its significance and the current status
of the research. Include the list of authors and their affiliations,
addresses, telephone and fax numbers, email addresses and the name of
the corresponding author. Please submit the extended abstract and foil
set by the deadline to: Deepu Talla via email at deepu@ti.com.
Program Co-chairs
-----------------
Deepu Talla deepu@ti.com Texas Instruments
Lizy John ljohn@ece.utexas.edu University of Texas at Austin
Program Committee
-----------------
Shuvra Bhattacharrya University of Maryland
Steve Carr Michigan Technological University
Pradeep Dubey Intel Corp
Jose Fridman Analog Devices
Jason Fritts Washington University in St. Louis
Tor Jeremiassen Texas Instruments
Lizy John University of Texas at Austin
Eugene John University of Texas at San Antonio
Trevor Mudge University of Michigan
John Reekie University of Technology Sydney
Deepu Talla Texas Instruments
Kees Vissers University of California at Berkeley
Past Workshops
--------------
ODES1: http://www.ece.vill.edu/~deepu/odes/odes-1_program.html
----------------------------------------------------------------------
----------------------------------------------------------------------
* New papers published online by Computer Architecture Letters
Computer Architecture Letters announces our four most recent papers,
which are publicly available at
http://www.comp-arch-letters.org/2003paps.html. We continue to seek new
submissions and remain committed to fast and accurate review. Our mean
time to decision remains one month, with an acceptance rate of
approximately 21%. For more information on submission, please see
http://www.comp-arch-letters.org
- A. Milenkovic, M. Milenkovic. "Stream-Based Trace Compression." Volume
2, Sep. 2003.
- C. Zhang, F. Vahid, J. Yang, W. Najjar. "A Way-Halting Cache for
Low-Energy High-Performance Systems." Volume 2, Sep. 2003.
- A. Cohen, L. Finkelstein, A. Mendelson, R. Ronen, D. Rudoy. "On
Estimating Optimal Performance of CPU Dynamic Thermal Management."
Volume 2, Oct. 2003.
- A. Cristal, J. F. Martinez, J. Llosa, M. Valero. "A Case for
Resource-conscious Out-of-order Processors." Volume 2, Oct. 2003.
Abstracts
---------
A. Milenkovic, M. Milenkovic. "Stream-Based Trace Compression." Volume
2, Sep. 2003.
Abstract:
Trace-driven simulation has long been used in both
processor and memory studies. The large size of traces motivated
different techniques for trace reduction. These techniques often
combine standard compression algorithms with trace-specific
solutions, taking into account the tradeoff between reduction in
the trace size and simulation slowdown due to decompression.
This paper introduces SBC, a new algorithm for instruction and
data address trace compression based on instruction streams. The
proposed technique significantly reduces trace size and
simulation time, and it is orthogonal to general compression
algorithms. When combined with gzip, SBC reduces the size of
SPEC CPU2000 traces 94-71968 times.
C. Zhang, F. Vahid, J. Yang, W. Najjar. "A Way-Halting Cache for
Low-Energy High-Performance Systems." Volume 2, Sep. 2003.
Abstract:
We have designed a low power four-way set-associative cache that stores
the four lowest-order bits of all way?s tags into a fully associative
memory, which we call the halt tag array. The comparison of the halt tag
array with the desired tag occurs concurrently with the address decoding
that determines which tag and data ways to read from. The halt tag array
pre-determines most tags that cannot match due to their low-order four
bits mismatching. Further accesses to ways with known mismatching tags
are then halted, thus saving power. Our halt tag array has the
additional feature of using static logic only, rather than dynamic logic
used in highly-associative caches, making our cache consumes even less
power. Our result shows 55% savings of memory access related energy over
a conventional four-way set-associative cache. We show nearly 2x energy
savings compared with highly associative caches, while imposing no
performance overhead and only 2% cache area overhead.
A. Cohen, L. Finkelstein, A. Mendelson, R. Ronen, D. Rudoy. "On
Estimating Optimal Performance of CPU Dynamic Thermal Management."
Volume 2, Oct. 2003.
Abstract:
In this paper we focus on dynamic thermal management
(DTM) strategies that use dynamic voltage scaling (DVS)
for power control. We perform a theoretical analysis targeted at
estimating the optimal strategy, and show two facts: (1) when
there is a gap between the initial and the limit temperatures,
it is best to start with a high (though not necessarily maximal)
frequency and decrease it exponentially until the limit temperature
is reached; (2) when being close to the limit temperature,
the best strategy is to stay there. We use the patterns exhibited
by the optimal strategy in order to analyze some existing DTM
techniques.
A. Cristal, J. F. Martinez, J. Llosa, M. Valero. "A Case for
Resource-conscious Out-of-order Processors." Volume 2, Oct. 2003.
Abstract:
Modern out-of-order processors tolerate long-latency memory operations
by supporting a large number of in-flight instructions. This is achieved
in part through proper sizing of critical resources, such as register
files or instruction queues. In light of the increasing gap between
processor speed and memory latency, tolerating upcoming latencies in
this way would require impractical sizes of such critical resources.
To tackle this scalability problem, we make a case for
resource-conscious out-of-order processors. We present quantitative
evidence that critical resources are increasingly underutilized in these
processors. We advocate that better use of such resources should be a
priority in future research in processor architectures.
----------------------------------------------------------------------
----------------------------------------------------------------------
* HotLeakage v1.0 release
We would like to announce the release of "HotLeakage" -- an
architectural model for subthreshold and gate leakage that we have
developed here at the University of Virginia. The most important
features of HotLeakage are the explicit inclusion of temperature,
voltage, gate leakage, and parameter variations, and the ability to
recalculate leakage currents dynamically as temperature and voltage
change due to operating conditions, DVS, etc. HotLeakage provides
default settings from BSIM3 and BSIM4 data for 180nm through 70nm
technologies for modeling caches and other structures, and provides a
simple interface for selecting alternate parameter values and for
modeling alternative microarchitecture structures. HotLeakage also
provides SimpleScalar models for several extant cache leakage control
techniques (namely gated-Vss, drowsy cache, and MTCMOS/RBB), with an
interface for adding further techniques. HotLeakage is currently a
semi-independent module for use with SimpleScalar. Because it is a
distinct module with its own interface, it should be fairly easy to port
to other simulators.
Because sub-threshold leakage currents are exponentially dependent on
temperature and voltage, because gate leakage is growing so rapidly, and
because parameter variations can have a profound effect on simulation
accuracy, we hope that HotLeakage will serve as a useful tool for
microarchitects to more accurately evaluate issues pertaining to leakage
power.
More information can be found on the HotLeakage website at
http://lava.cs.virginia.edu/HotLeakage
We maintain a mailing list for user questions and feedback, which can be
subscribed to at the same website.
Kevin Skadron, Mircea R. Stan, Dharmesh Parikh, Yan Zhang, Yingmin Li,
and Karthik Sankaranarayanan
Depts. of Computer Science, Electrical and Computer Engineering
University of Virginia
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