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SIGARCH-MSG: October 2003 Digest of SIGARCH Messages
This is the October 2003 Digest of SIGARCH Messages (sigarch-oct03):
* ISCA 2004 Call for Papers
http://isca.in.tum.de/
Submitted by Ricardo Bianchini <ricardob@cs.rutgers.edu>
* IEEE TPDS Special Issue on On-Chip Networks
http://www.computer.org/mc/tpds/author.htm
Submitted by Li-Shiuan Peh <peh@ee.princeton.edu>
* SIGMETRICS 2004 Call for Papers
http://www.cs.columbia.edu/~sigm2004/
Submitted by Jason Nieh <nieh@cs.columbia.edu>
* ICS 2004 Call for papers
http://graal.ens-lyon.fr/ICS04/
Submitted by Liviu Iftode <iftode@cs.umd.edu>
* HPCA 2004 Workshops Announced
http://www.csl.cornell.edu/~espeight/hpca10wkshps.html
Submitted by Mark Heinrich <heinrich@cs.ucf.edu>
* Workshop on Communication Architecture for Clusters (CAC '04) Call For Papers
http://www.cis.ohio-state.edu/~cac
Submitted by Nectarios Koziris <nkoziris@cslab.ece.ntua.gr>
* 2nd Workshop on Network Processors & Applications - NP3 Call for Papers
http://www.cse.wustl.edu/NP3/
Submitted by Haldun Hadimioglu <haldun@photon.poly.edu>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org
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Doug Burger Office: 3.432 ACES
Assistant Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
University of Texas at Austin Fax: 512-232-1413
Taylor Hall 2.124 E-mail: dburger@cs.utexas.edu
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* ISCA 2004 Call for Papers
ISCA-2004 Call for Papers
The 31st Annual International Symposium on Computer Architecture
Munich, Germany, June 19-23, 2004
http://isca.in.tum.de/
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Papers are solicited for the 31st Annual International Symposium on
Computer Architecture. Papers are being sought on all aspects of
computer architecture, including (but not limited to) the following:
* Processor architectures
* Memory hierarchy subsystems
* Multiprocessors and multicomputers
* Storage and interconnect subsystems
* Application-specific, reconfigurable, and embedded architectures
* Power-efficient architecture
* Dependable architectures
* Impact of technology on architecture
* Impact of application characteristics on architecture
* Architectures for emerging technologies and applications
* Performance/power evaluation and measurement of real systems
The DEADLINE for abstract submissions (300 - 600 words) is OCTOBER 31,
2003 at 11.59PM PST (US). FULL PAPERS are due on November 7, 2003 at
11.59PM PST (US). NO EXTENSION WILL BE GRANTED!!! NOTIFICATION of
acceptance/rejection will be given on FEBRUARY 17, 2004. FINAL
VERSIONS of the accepted papers are due on MARCH 24, 2004.
As in previous years, a series of tutorials and workshops will be held
immediately preceding the symposium. Tutorial and workshop proposals
will be accepted until November 14, 2003. If you wish to organize a
tutorial (1/2 or 1 day), e-mail a proposal to the Tutorials Chair
(Timothy Pinkston, tpink@charity.usc.edu), including title, brief
description of topics to be covered, and bio of the speakers. If you
wish to organize a workshop (1 or 2 days), e-mail a proposal to the
Workshops Chair (Sally A. McKee, sam@csl.cornell.edu), including
title, brief description of topics to be covered, and bio of the
organizers. Notification of tutorial and workshop decisions will be
emailed back to authors on December 15, 2003.
Summary of important dates:
Abstract submission deadline: Oct 31, 2003
Paper submission deadline: Nov 7, 2003
Workshop/tutorial proposal deadline: Nov 14, 2003
Workshop/tutorial proposal notification: Dec 15, 2003
Paper acceptance notification: Feb 17, 2004
Final paper due: Mar 24, 2004
Please refer to http://isca.in.tum.de for the complete call for
papers and other details about the symposium.
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* IEEE TPDS Special Issue on On-Chip Networks
Call for Papers
IEEE Transactions on Parallel and Distributed Systems
Special Issue on On-Chip Networks
IEEE Transactions on Parallel and Distributed Systems is seeking original
manuscripts for a Special Issue on On-Chip Networks, scheduled to be
published in February, 2005.
As the scale of chip integration continues to advance at a fast pace, the
issue of how to fully utilize burgeoning silicon resources and increasing
clock frequencies becomes more and more important. This issue is further
complicated as the need to tolerate ever increasing chip-crossing
interconnect delays and power consumption reaches criticality. System
designers are finding the on-chip interconnect to be one of the more
challenging and significant design problems facing them the near term.
This represents a research area that is only just recently being
pursued rigorously. Articles for this special issue are solicited that
describe fundamental research and experiences covering architectural and
design aspects related to this problem.
Topics of interest include, but are not limited to the following:
- Design methodologies and abstractions for networks-on-chip
- On-chip network architectures: topologies, switching, routing, flow
control, and microarchitecture issues
- On-chip network technology: nanotechnology and nanoscale designs
- Scalar operand networks and operand matching algorithms
- On-chip networks crossing the memory hierarchy and I/O
- Implications of CMP, partitioned, and cluster architectures on on-chip
network design
- Networks-on-chip for embedded systems, application-specific architectures,
integrated IP cores and systems-on-a-chip (SoCs)
- Application/software interfaces to networks-on-chip
- Power/Energy-efficient on-chip networks
- Reliability and reconfigurability issues for on-chip networks
- Circuit and timing issues for on-chip networks
Submitted articles must not have been previously published or currently
submitted for journal publication elsewhere. As an author, you are
responsible for understanding and adhering to our submission guidelines.
You can access them by clicking on http://www.computer.org/mc/tpds/author.htm.
Please thoroughly read these before submitting your manuscript.
Please submit your paper to Manuscript Central at
http://cs-ieee.manuscriptcentral.com/.
Please feel free to contact the Peer Review Supervisor, Suzanne Werner at
<swerner@computer.org> or the guest editors at peh@ee.princeton.edu or
tpink@charity.usc.edu if you have any questions.
Please note the following important dates:
Manuscript Submission Deadline: Jan. 30, 2004
Reviews Completed: Apr. 30, 2004
Major Revisions Due (if needed): June 30, 2004
Reviews of Revisions Completed (if needed): July 30, 2004
Minor Revisions due (if needed): Aug. 15, 2004
Notification of Final Acceptance: Aug. 20, 2004
Final Manuscripts Due: Sept. 10, 2004
Publication Date: February 2005
Guest Editors:
Li-Shiuan Peh Timothy Mark Pinkston
Assistant Professor of EE Associate Professor of EE-Systems
Princeton University University of Southern California
peh@ee.princeton.edu tpink@charity.usc.edu
tel: 1-609-258-7747 tel: 1-213-740-4482
http://ww.ee.princeton.edu/~peh http://www.usc.edu/dept/ceng/pinkston/SMART.html
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* SIGMETRICS 2004 Call for Papers
Call for Papers
******SIGMETRICS 2004/ Performance 2004 ******
Joint International Conference on
Measurement and Modeling of Computer Systems
Sponsored by ACM SIGMETRICS and IFIP Working Group 7.3
June 12-16th, 2004, New York, NY
http://www.cs.columbia.edu/~sigm2004/
The joint SIGMETRICS/Performance conference solicits papers on the
development and application of state-of-the-art, broadly applicable
analytic, simulation, and measurement-based performance evaluation
techniques. Of particular interest is work that furthers the
state-of-the-art in performance evaluation methods, or combines
analytic and experimental methods to evaluate design trade-offs in real
systems.
Topics of interest include but are not limited to:
- Performance-oriented design and evaluation studies of communication
networks, Internet servers, computer architectures, database
systems, operating systems, distributed systems, multimedia systems,
mobile and handheld systems, file and I/O systems, memory systems,
real-time systems, and dependable systems, including case studies
and performance-evaluation tools.
- Performance methodology techniques, algorithms, and tools for
analytic modeling, system measurement and monitoring, model
verification and validation, workload characterization, simulation,
statistical analysis, stochastic modeling including queues,
stochastic Petri nets, stochastic process algebras, model checking,
experimental design, reliability and availability analysis, power
analysis, performance optimizations, and hybrid models.
Submission Guidelines
=====================
- Papers: Detailed submission guidelines are available at the
conference web site.
- Hot Topic Sessions: Proposals are solicited for a hot topic session,
in which a group of speakers will present and discuss their recent
results in an area. Send proposals to the program chairs,
identifying the organizer of the session, the session title, three
to five speakers, the titles of their talks, and a short abstract of
each talk.
- Tutorials: A series of tutorials will immediately precede the main
conference. Send proposals of no more than 1 or 2 pages (for
90-minute or 3-hour tutorials) to the tutorials chair. Include the
proposed title, brief description of material, intended audience,
assumed background of attendees, and the name, affiliation, contact
information (e-mail and phone), and brief biography of speaker(s).
Postscript or PDF is preferred.
Important Dates:
================
November 2, 2003: Paper title, abstract, and author affiliations due.
November 7, 2003: Full papers, tutorials, and hot topic proposals due
(HARD deadline, no extensions)
January 29, 2004: Notification of acceptance
For more and up to date information see the conference web site
at: http://www.cs.columbia.edu/~sigm2004/.
Organization
============
General Chair:
E. G. Coffman, Jr. (Columbia University) egc@ee.columbia.edu
Program Co-Chairs:
Zhen Liu (IBM Research) zhenl@us.ibm.com
Arif Merchant (HP Labs) arif@hpl.hp.com
Local Arrangement Chair:
Vishal Misra (Columbia University) misra@cs.columbia.edu
Tutorials Chair:
Li Zhang (IBM Research) zhangli@us.ibm.com
Proceedings Chair:
Yefim Shuf (IBM Research) yefim@us.ibm.com
Publicity Chair:
Jason Nieh (Columbia University) nieh@cs.columbia.edu
Finance Chair:
Sambit Sahu (IBM Research) sambits@us.ibm.com
Web Masters:
Angelos Stavrou (Columbia University) angelos@ee.columbia.edu
Hanhua Feng (Columbia University) hanhua@cs.columbia.edu
Program Committee:
Ajmone-Marsan, Marco Politecnico di Torino, Italy
Baccelli, Francois ENS, France
Barford, Paul U. Wisconsin, USA
Bershad, Brian U. Washington, USA
Biersack, Ernst Eurecom, France
Bonald, Thomas France Telecom, France
Borst, Sem CWI, Netherlands
Cao, Pei Cisco, USA
Chang, Cheng-Shang National Tsing Hua Univ. Taiwan
Chase, Jeff Duke University, USA
Cherkasova, Lucy HP Labs, USA
de Souza e Silva, Edmundo UFRJ, Brazil
Douceur, John Microsoft Research, USA
Duffield, Nick AT&T Research, USA
Eager, Derek U Saskatchewan, Canada
Golubchik, Leana USC, USA
Harchol-Balter, Mor Carnegie Mellon University, USA
Jean-Marie, Alain Uni Montpellier, France
Keeton, Kimberly HP Labs, USA
Kumar, Anurag IISc, India
Kurose, Jim Univ. Massachusetts, USA
LeBoudec, Jean-Yves EPFL, Switzerland
Long, Darrell UCSC, USA
Lui, John Chinese U. of Hong Kong, China
Mazumdar, Ravi Purdue University, USA
Misra, Vishal Columbia University, USA
Mitra, Debasis Bell Laboratories, USA
Muntz, R.Richard UCLA, USA
Nahum, Erich IBM Research, USA
Nain, Philippe INRIA, France
Nieh, Jason Columbia University, USA
Ross, Keith Brooklyn Poly University, USA
Sanders, William UIUC, USA
Setia, Sanjeev George Mason Univ., USA
Shenoy, Prashant Univ. Massachusetts, USA
Smirni, Evgenia College of William & Mary, USA
Squillante, Mark IBM Research, USA
Srikant, Rayadurgam UIUC, USA
Towsley, Don Univ. Massachusetts, USA
Tripathi, Satish UC at Riverside, USA
Verscheure, Olivier IBM Research, USA
Vernon, Mary U Wisconsin-Madison, USA
Williamson, Carey University of Calgary, Canada
Woodside, Murray C. Carleton University, Canada
Xia, Cathy IBM Research, USA
Yao, David Columbia University, USA
Zhang, Zhi-Li U Minnesota, USA
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* ICS 2004 Call for papers
See it at http://graal.ens-lyon.fr/ICS04/
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* HPCA 2004 Workshops Announced
The following excellent set of workshops will be held in conjunction with HPCA-10 in Madrid, Spain on February 14th and 15th, 2004. Please check the individual workshop home pages for submission guidelines and deadlines, or the HPCA Workshop page at http://www.csl.cornell.edu/~espeight/hpca10wkshps.html, and remember to register for the Workshops when you register for HPCA!
February 14th
-------------
WEPA 1: Embedded Parallel Architectures (http://www.kayamba.com/~enric/wepa-1.htm)
NP3: Network Processors (http://www.cse.wustl.edu/NP3/)
SAN 3: System Area Networks (http://www.cse.ogi.edu/SAN-3/)
PPEC 1: Productivity and Performance in High-End Computing (http://www.research.ibm.com/people/r/rajamony/pphec.html)
February 15th
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CAECW 7: Computer Architecture Evaluation Using Commercial Workloads (http://tesla.hpl.hp.com/caecw04/)
INTERACT 8: Interaction Between Compilers and Computer Architecture (http://api.ece.uic.edu/workshop/interact.htm)
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* Workshop on Communication Architecture for Clusters (CAC '04) Call For Papers
To be held in Conjunction with
Int'l Parallel and Distributed Processing Symposium (IPDPS '04)
Santa Fe, New Mexico Eldorado Hotel, April 26-30, 2004
http://www.cis.ohio-state.edu/~cac
Title and Abstract: October 30, 2003
Paper submission: November 3, 2003
Notification of acceptance: December 19, 2003
Camera-ready due: January 23, 2004
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web page http://www.cis.ohio-state.edu/~cac
Call For Papers
THEME:
The availability of commodity PCs/workstations and high-speed networks
(Local
Area Networks and System Area Networks) at low prices enabled the
development of
low-cost clusters. These clusters are being targeted for support of
traditional
high-end computing applications as well as emerging applications,
especially
those requiring high-performance servers. Designing high-performance and
scalable clusters for these emerging applications requires design and
development of high-performance communication and I/O subsystems,
low-overhead
programming environment support and support for Quality of Service
(QoS). New
standards such as InfiniBand Architecture (IBA) and PCI Express AS, and
availability of high-speed networking products (Myrinet, Quadrics, IBA
4X, and
10GigEthernet) are providing exciting ways to design high-performance
communication and I/O architectures for clusters.
A large number of research groups from academia, industry, and research
labs are
currently engaged in the above research directions. The goal of this
workshop is
to bring together researchers and practitioners working in the areas of
communication, I/O, and architecture to discuss state-of-the-art
solutions as
well as future trends for designing scalable, high-performance, and
cost-effective communication and I/O architectures for clusters.
The first three workshops in this series (CAC '01, CAC '02, and CAC '03)
were
held in conjunction with IPDPS conferences, and they were very
successful. The
CAC '04 workshop plans to continue this tradition.
TOPICS OF INTEREST:
Topics of interest for the workshop include but are not limited to:
Router/switch, network, and network-interface architecture for
supporting
efficient point-to-point communication, collective communication, and
I/O at
intra-cluster and inter-cluster levels.
Design, development, and implementation of low-level communication and
I/O
protocols (GM, TCP/IP, VAPI, SDP, DAPL, SRP, iSCSI, RDMA over IP, etc)
on
different networking and interconnect technologies (such as Myrinet,
10Gigabit
Ethernet, InfiniBand, Quadrics, TCP Offload Engine, etc.).
High-performance implementation of different programming layers (Message
Passing Interface (MPI), Distributed Shared Memory such as TreadMarks,
Get/Put, Global Arrays, sockets, etc.) and File Systems (such as PVFS
and
DAFS).
Communication and architectural issues related to switch organization,
flow
control, congestion control, routing and deadlock-handling, load
balancing,
reliability, and QoS support.
Strategies, algorithms, and protocols for management of communication
resources, including topology discovery, hot update/replacement of
components,
dynamic reconfigurations, etc.
Performance evaluation and tools for different application areas,
including
interprocessor communication and I/O, etc.
Results of both theoretical and practical significance will be
considered.
PROCEEDINGS:
The proceedings of this workshop will be published together with the
proceedings
of other IPDPS '04 workshops by the IEEE Computer Society Press.
PAPER SUBMISSIONS:
We are planning a purely web submission and review process. Authors are
requested to submit papers (in PDF format) not exceeding 10
single-spaced pages,
including abstract, five key words, contact address, figures, and
references.
Detailed instructions on web submissions will be available soon.
Note: the PDF file must be viewable using the ``acroread'' tool. It is
also
important, when creating your PDF file, to use a page size of 8.5x11
inches
(LETTER sized output not A4), since an A4 sized page may be truncated on
a
LETTER sized printer.
SCHEDULE:
Title and Abstract: October 30, 2003
Paper submission: November 3, 2003
Notification of acceptance: December 19, 2003
Camera-ready due: January 23, 2004
WORKSHOP CO-CHAIRS:
Dhabaleswar K. Panda (Ohio State), Jose Duato (Tech. Univ. of Valencia,
Spain),
and Craig Stunkel (IBM TJ Watson Research Center)
PROGRAM COMMITTEE:
Bulent Abali (IBM TJ Watson)
Mohammad Banikazemi (IBM TJ Watson)
Angelos Bilas (Univ. of Toronto, Canada)
Alan Benner (IBM)
Ron Brightwell (Sandia National Lab)
Darius Buntinas (Argonne National Lab)
Toni Cortes (UPC, Spain)
Wu-Chun Feng (Los Alamos National Lab)
Jose Flich (Tech. Univ. of Valencia, Spain)
Mitchell Gusat (IBM, Zurich)
Mark Heinrich (Univ. of Central Florida)
Manolis G.H. Katevenis (FORTH and Univ. of Crete, Greece)
Nectarios G. Koziris (National Technical Univ. of Athens, Greece)
Mario Lauria (Ohio State)
Olav Lysne (Univ. of Oslo, Norway)
Arthur (Barney) Mccabe (Univ. of New Mexico)
Pankaj Mehra (HP)
Shubu Mukherjee (Intel)
Jarek Nieplocha (Pacific Northwest National Lab)
Scott Pakin (Los Alamos National Lab)
Fabrizio Petrini (Los Alamos National Lab)
Greg Pfister (IBM)
Timothy Pinkston (Univ. of Southern California)
Wolfgang Rehm (Tech. Univ. of Chemnitz, Germany)
Antonio Robles (UPV, Spain)
Tom Rokicki (Instantis)
Reza Rooholamini (Dell)
Evan Speight (Cornell Univ.)
Thomas M. Stricker (ETH, Zurich, Switzerland)
Peter Varman (NSF and Rice Univ.)
Pete Wyckoff (Ohio Supercomputer Center)
Mazin Yousif (Intel)
PUBLICITY COORDINATORS:
Darius Buntinas (Argonne National Lab) and Nectarios G. Koziris
(National
Technical Univ. of Athens, Greece)
ADDITIONAL INFORMATION:
For further questions, send e-mail to cac@cis.ohio-state.edu.
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* 2nd Workshop on Network Processors & Applications - NP3 Call for Papers
*********************************************************************
2nd CALL FOR PAPERS
*********************************************************************
Workshop on Network Processors & Applications - NP3
http://www.cse.wustl.edu/NP3/
February 14-15, 2004
Madrid, Spain
Held in conjunction with HPCA 10 - The 10th International
Symposium on High-Performance Computer Architecture
http://www.ac.uma.es/hpca10/
February 14-18, 2004
OVERVIEW
As the performance and importance of digital communication networks
have increased, so have the challenges in network component design. To
meet ever-escalating performance, flexibility and economy
requirements, the networking industry has opted to build products
around network processors. These processors are programmable yet
application-specific; their designs are tailored to efficiently
implement communications applications such as: routing, protocol
analysis, voice and data convergence, firewalls, VPNs, and QoS. The
term network processor is used here in the most generic sense -- from
task-specific processors, such as classification and encryption
engines, to more general-purpose packet or communications processors.
Network processor design is an emerging field with numerous challenges
and opportunities. The goal of this workshop is to provide a forum for
engineers and scientists from academia and industry to discuss their
latest research in the architecture, design, programming, and use of
these devices. We are especially interested in attracting new or
experimental techniques and approaches.
IMPORTANT DATES
Submissions due: November 3
Author notifications: December 22
Final papers due: January 9
TOPICS
Topics of particular interest include, but are not limited to:
* Architectures for network, communications, or packet processors
* Network processor theory of design
* Novel commercial product designs
* Search engines
* Benchmarking and performance analysis
* Coprocessors such as CAMs and other support devices
* Interfaces to high-speed packet buses and switch fabrics
* Techniques for accelerating network services
* Voice processing and packet telephony
* Software aspects of programming processors for networking
* Applications, including packet forwarding, packet classification,
QoS, encryption and security, compression, etc.
The workshop will consist of a keynote address, paper presentations
and a panel session. In addition to academic and research
contributions, product descriptions that focus on architecture
(hardware or software) or performance analysis will also be
considered. Attendees will receive a copy of workshop papers.
SUBMISSIONS
Please submit full papers (single spaced, font size 11, 1 inch
margins, not exceeding 15 pages) in Adobe PDF format for review to
pcrowley@cse.wustl.edu.
PROGRAM COMMITTEE
Alan Berenbaum, Agere
Brad Calder, UCSD
Andrew Campbell, Columbia University
Patrick Crowley, Washington University in St. Louis
Jordi Domingo, UPC (Spain)
Mark Franklin, Washington University in St. Louis
Jorge Garcia, UPC (Spain)
Haldun Hadimioglu, Polytechnic University
Marco Heddes, Transwitch Corporation
Manolis Katevenis, University of Crete (Greece)
Bill Mangione-Smith, UCLA
Kenneth Mackenzie, Reserviour Labs
John Marshall, Cisco
Daniel Mlynek, EPFL (Switzerland)
Peter Z. Onufryk, IDT
Lothar Thiele, ETH Zürich (Switzerland)
Jon Turner, Washington University in St. Louis
Mateo Valero, UPC (Spain)
Tilman Wolf, University of Massachusetts
Raj Yavatkar, Intel
ORGANIZERS
Patrick Crowley, Washington University in St. Louis (pcrowley@cse.wustl.edu)
Mark Franklin, Washington University in St. Louis (jbf@ccrc.wustl.edu)
Haldun Hadimioglu, Polytechnic University (haldun@photon.poly.edu)
Peter Z. Onufryk, IDT (peter.onufryk@idt.com)
NP2 at HPCA 9 (2003)
http://www.cs.washington.edu/NP2/
Selected papers from NP2 and additional industry contributions will
appear in Network Processor Design : Issues and Practices Volume II
(Morgan Kaufmann Publishers, October 2003).
NP1 at HPCA 8 (2002)
http://www.cs.washington.edu/NP1/
Selected papers from NP1 and additional industry contributions appear
in Network Processor Design : Issues and Practices Volume I
http://www.mkp.com/books_catalog/catalog.asp?ISBN=1-55860-875-3
(Morgan Kaufmann Publishers, September 2002).
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