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SIGARCH-MSG: June 2002 Digest of SIGARCH Messages
This is the June 2002 Digest of SIGARCH Messages (sigarch-jun02):
* Guidelines for SIGARCH Sponsored Conferences
http://www.acm.org/sigarch/conference_guidelines.html
Submitted by Mark D. Hill <markhill@cs.wisc.edu>
* 9th Int'l Symposium on High Performance Computer Architecture (HPCA)
Call for Papers: http://www.cs.arizona.edu/hpca9/
Submitted by Soner Onder <soner@mtu.edu>
* MEDEA 2002 Workshop
Call for papers: http://garga.iet.unipi.it/medea
Submitted by Sandro Bartolini <s.bartolini@iet.unipi.it>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org
* Archive: http://www.cs.wisc.edu/~lists/archive/sigarch-members/maillist.html
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail listserv@acm.org with message body: unsubscribe SIGARCH-MEMBERS
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Doug Burger Office: 3.432 ACES
Assistant Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
University of Texas at Austin Fax: 512-232-1413
Taylor Hall 2.124 E-mail: dburger@cs.utexas.edu
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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Guidelines for SIGARCH Sponsored Conferences
David A. Patterson
Computer Science Division /EECS Dept.
University of California, Berkeley
April 20, 1994
http://www.acm.org/sigarch/conference_guidelines.html
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* *
* HPCA-9 *
* *
* Call for Papers *
* *
* Ninth International Symposium on High Performance *
* Computer Architecture *
* *
* Anaheim, California. Feb. 8-12, 2003 *
* *
* http://www.cs.arizona.edu/hpca9/ *
* *
* *
* Important Dates *
* *
* Paper submission deadline : July 12, 2002 *
* Workshop proposals due : July 12, 2002 *
* Author Notification : Oct. 1, 2002 *
* Camera ready copy due : Nov. 3, 2002 *
* *
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The International Symposium on High-Performance Computer Architecture
provides a high quality forum for scientists and engineers to present
their latest research findings in this rapidly changing field. Authors
are invited to submit full papers on all aspects of high-performance
computer architecture. Topics of interest include, but are not limited
to:
* Processor architectures
* Cache and memory architectures
* Parallel computer architectures
* Impact of VLSI scaling techniques
* Novel architectures for emerging applications
* Power-efficient architectures
* High-availability architectures
* High-performance I/O architectures
* Embedded and reconfigurable architectures
* Real-time architectures
* Interconnection networks and network interfaces
* Innovative hardware/software trade-offs
* Simulation and performance evaluation
* Benchmarking and measurements
Please check the following web site for paper submission information:
http://www.cs.arizona.edu/hpca9/
The submission should not exceed 6000 words. Papers that exceed the
length limit or that cannot be viewed using Adobe Acrobat Reader
(version 3.0 or higher) may not be reviewed. The official submission
deadline is July 12, 2002 (Midnight EST, USA). An automatic extension
of one week will be given without request. No further extensions will be
given. Papers may be submitted for blind review at the option of the
authors. Please indicate whether the paper is a student paper for best
student paper nominations. Please submit proposals for workshops to the
workshop chair by July 12, 2002.
Important Dates
Paper submission deadline : July 12, 2002
Workshop proposals due : July 12, 2002
Author Notification : Oct. 1, 2002
Camera ready copy due : Nov. 3, 2002
General Chairs
Nader Bagherzadeh, Univ. of California, Irvine
Laxmi N. Bhuyan, Univ. of California, Riverside
Steering Committee
Dharma P. Agrawal, Univ. of Cincinnati
Laxmi N. Bhuyan, Univ. of California, Riverside
Yale Patt, Univ. of Texas at Austin
Jean-Luc Gaudiot, Univ. of California, Irvine
Joel Emer, Intel
David Kaeli, Northeastern Univ.
Pen-Chung Yew, Univ. of Minnesota
David Lilja, Univ. of Minnesota
Program Chair
Rajiv Gupta, Univ. of Arizona
Program Committee
Todd Austin, Univ. of Michigan
Pradip Bose, IBM
Doug Burger, Univ. of Texas at Austin
Brad Calder, Univ. of California, San Diego
Dan Connors, Univ. of Colorado Tom Conte, NC State Univ.
Darren Cronquist, HP Labs
Chita Das, Penn State Univ.
Sandhya Dwarkadas, Univ. of Rochester
Marius Evers, AMD
Kanad Ghose, SUNY Binghamton
Antonio Gonzalez, UPC, Barcelona
James Goodman, Univ. of Wisconsin
Wei-Chung Hsu, Univ. of Minnesota
Yiming Hu, Univ. of Cincinnati
Stephen Jenks, Univ. of California, Irvine
Steve Melvin, Flowstorm
Walid Najjar, Univ. of California, Riverside
Soner Onder, Michigan Technological Univ.
Santosh Pande, Georgia Tech
Sanjay Patel, UIUC
Li-Shiuan Peh, Princeton University
Timothy Mark Pinkston, USC
Ronny Ronen, Intel, Israel
John Shen, Intel, MRL
Josep Torrellas, UIUC
Mateo Valero, UPC, Barcelona
Jie Wu, Florida Atlantic Univ.
Yuanyuan Yang, SUNY at Stony Brook
Local Arrangements Chair
Stephen Jenks, Univ. of California, Irvine
Workshop Chair
Walid Najjar, Univ. of California, Riverside
Publications Chair
Li-Shiuan Peh, Princeton Univ.
Finance and Registration Chair
Nayla Nassif, Univ. of California, Irvine
Publicity Chair
Soner Onder, Michigan Technological Univ.
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If you have any questions about HPCA-9, please do not hesitate to
contact soner@mtu.edu.
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Call For Papers: MEDEA Workshop
MEDEA 2002 web site: http://garga.iet.unipi.it/medea
On Chip MultiProcessor: Processor Architecture and Memory Hierarchy
related Issues
held in conjuction with PACT 2002 Conference
September 22-25, 2002, Charlottesville, Virginia, USA
"Medea (On Chip Multiprocessor tecniques) helps Jason (nowdays
microprocessors design). Will Medea kill Jason's sons?"
Call for Paper
Scope and Motivation
MEDEA-2002 aims to continue the high level of interest in the first two
MEDEA Workshops held with PACT'00 and PACT'01.
In the previous versions MEDEA (MEmory access DEcoupled Architectures)
focused on Access Decoupling, Thread Level Parallelism, ILP, Latency
tolerating techniques and related issues.
Currently, there is a great interest in On-Chip Multiprocessors both for
general purpose and embedded systems. Moreover, there is a growing
interest in the resource clusterization, mu
ltithreading, Thr
ead and Instruction Level Parallelism, power consumption, latency
reducing techniques and workload characterizations.
The MEDEA-2002 Workshop wants to be a forum for academic and industrial
people to meet, discuss and exchange their ideas and experience on
On-Chip Multiprocessor issues, solutions, challenges, both in the
technical, general purpose and in the embedded horizon. MEDEA-2002 is
seeking submissions describing ideas and experience with On Chip
Multiprocessor systems and solutions from other fields applicable to
them.
The format of the workshop will include presentations of selected papers
and discussion after each presentation.
Accepted papers appear in a special issue of the ACM SigArch Computer
Architecture News. The workshop committee may invite authors to extend
their papers for inclusion in the special issue.
Topics of Interest
On-chip Multiprocessors (OCM)
- architectures
- issues
- solutions
- multithreading
-
cache and memo
ry sub-systems
- coherence protocols
- development tools
- applications
- power consumption
- solutions for embedded, commercial, scientific and technical
workloads
- performance evaluation
- optimization
Academic and Industrial Experience in OCM
- high performance
- general purpose
- embedded
Code optimization techniques
Memory Access Decoupling
Processor Architecture
Latency Tolerance and Reduction techniques
Instruction Level and Thread Level Parallelism
System on Chip
Workload characterization
Information for Authors
The papers should be at most 10 pages in length. The abstracts and
papers should be submitted in either postscript or PDF format by email
to the workshop-organizing members: Pierfrancesco Foglia and Sandro
Bartolini.
Paper should be written in standard IEEE format for conference
proceedings. Hard copy (postal) submissions will not be accepted.
Please email submiss
ions by July, 10 20
02. You receive an acknowledgment of your submission by the following
week. Authors will be notified of acceptance or rejection by August 1,
2002 and the final papers are due by August 7, 2002.
To speed-up the reviewing process, we encourage also submission of
abstract by July, 3 2002.
All submissions will be refereed, and informal proceedings will be
printed and distributed at the workshop. Accepted papers appear in a
special issue of the ACM SigArch Computer Architecture News. The
workshop committee may invite authors to extend their papers for
inclusion in the special issue.
Important Dates
July, 3 2002 Abstract Submission
July, 10 2002 Paper Submission Deadline
August, 1 2002 Acceptance Notification
August, 7 2002 Final Papers Due
September, 22 2002 Workshop and PACT will start in Charlottesville,
Virginia
Registration and accomodation
Attendees are requested to go to the hosting PACT'02 conference to
perform the registrati
on to Medea-2002 and
make room reservations in the conference hotels. We strongly suggest
that you make your room reservation in advance and register before the
advance registration deadline to benefit from combined PACT'02/Medea'02
registration fees.
Organizing Committee
Sandro Bartolini, s.bartolini@iet.unipi.it
University of Pisa, Italy
Pierfrancesco Foglia, foglia@iet.unipi.it
University of Pisa, Italy
Cosimo Antonio Prete, prete@iet.unipi.it
University of Pisa, Italy
Program Commitee (in Progress)
Ali Hurson, hurson@cse.psu.edu
The Pennsylvania State University, PA, USA
Mateo Valero, mateo
@ac.upc.es
Uni
versidad Politecnica de Catalunya, Spain
Antonio Gonzalez, antonio@ac.upc.es
Universidad Politecnica de Catalunya, Spain
David Kaeli, kaeli@ece.neu.edu
Northeastern University, MA, USA
Veljko Milutinovic, vm@ubbg.etf.ac.yu
University of Belgrade, Serbia, YU
Ricardo Bianchini, ricardo@cos.ufrj.br
Federal University of Rio de Janeiro, Brazil
Avi Mendelson, avi.mendelson@intel.com
Intel, Israel
Liviu Iftode, iftode@cs.umd.edu
Maryland University, NJ, USA
Roberto Giorgi, giorgi@acm.org
University of Siena, Italy
Jelica Protic, jeca@sezampro.yu
University of Belgrade, Serbia, YU
Alessio Bechini, a.bechini@iet.unipi.it
Univeristy of Pisa, Italy
Mats Brorsson, Mats.Brorsson@imit.kth.se
Royal Institute of Technology in Stockholm, Sweden
Theo Ungerer, ungerer@informatik.uni-augsburg.de
University of Augsburg, DE,
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