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SIGARCH-MSG: Addendum to May 2002 Digest of SIGARCH Messages
Since I just don't want to go, I've attached are a few more messages
for the SIGARCH mailing list digest for May 2003 (grep sigarch-may02b):
* Workshop on Caching, Coherence, and Consistency (WC3 '02)
Call for Abstracts: http://www.cs.rutgers.edu/~wc3/
Submitted by Ricardo Bianchini & Liviu Iftode <wc3@cs.rutgers.edu>
* 9th Int'l Symposium on High Performance Computer Architecture (HPCA)
Call for Papers: http://www.cs.arizona.edu/hpca9/
Submitted by Soner Onder <soner@mtu.edu>
* Hot Chips 14: A Symposium on High-Performance Chips (slight correction)
Call for Participation: http://www.hotchips.org
Submitted by Allen Baum <hotchips@mindspring.com>
--Mark D. Hill
infodir_SIGARCH@acm.org
SIGARCH Information Director
* Archive: http://www.cs.wisc.edu/~lists/archive/sigarch-members/maillist.html
* Web pages: http://www.cs.wisc.edu/arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail listserv@acm.org with message body: unsubscribe SIGARCH-MEMBERS
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Mark D. Hill Office 6373 CSS
Professor & Romnes Fellow Phone 608-262-2196
Computer Sciences Department Asstnt 608-265-3402
University of Wisconsin-Madison FAX 608-262-9777
1210 West Dayton Street E-mail markhill@cs.wisc.edu
Madison, WI 53706-1685 USA http://www.cs.wisc.edu/~markhill
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Second Workshop on Caching, Coherence, and Consistency (WC3 '02)
June 22, 2002
in conjunction with the
16th Annual ACM International Conference on Supercomputing (ICS 2002)
New York, NY, USA
http://www.cs.rutgers.edu/~wc3/
Motivation
The workshop aims to bring together researchers from various areas of
computer science whose work is related to data caching, coherence, and
consistency. Interestingly, these three topics have been present in
the research agenda of several independent communities that usually do
not meet. The interest in these topics started in the computer
architecture community and now pervades in parallel and distributed
systems research. There have also been significant efforts to address
caching, coherence, and consistency topics using compiler, operating
system, or application support. The same topics have been addressed by
the operating system community in the context of file and storage
systems for both servers and mobile systems. More recently, the
interest in these issues has been revived by the web technologies,
including content and service replication and distribution.
This workshop is the first forum to bring together people from all
these areas of research by recognizing that their specific caching,
coherence, and consistency issues have common denominators that can
lead to fruitful discussions and exchange of ideas. The first edition
of this workshop, which took place in conjunction with ICS'01, was
very successful. This workshop continues the tradition of the
workshops on software DSM, which were associated with ICS in 1999 and
2000, but with a much broader scope.
Scope
We solicit abstracts of original research including, but not limited
to, the following areas:
* Memory caches
* Cache modeling and analysis
* Consistency models
* File and storage caching
* Caching, coherence, and consistency in shared-memory multiprocessors
* Caching, coherence, and consistency in clusters
* Caching, coherence, and consistency in peer-to-peer systems
* Caching, coherence, and consistency in mobile systems
* Web caching, coherence, and consistency
* Web content replication and distribution
Authors are invited to submit 5-page extended abstracts that
demonstrate original and unpublished research in the areas of data
caching, coherence, and consistency. Abstracts should be emailed to
wc3@cs.rutgers.edu in postscript or pdf format. Accepted papers can be
up to 10 pages long and will be published by the workshop. One of the
authors will be required to attend the workshop and present the work.
Important Dates
May 08, 2002: Extended abstracts due. (extended from May 01)
May 20, 2002: Notification sent to authors.
June 10, 2002: Camera-ready papers due.
Program Committee
Lorenzo Alvisi, University of Texas at Austin
Eduard Ayguade, UPC, Spain
Azer Bestavros, Boston University
Ricardo Bianchini, Rutgers University (co-chair)
Enrique V. Carrera, Rutgers University
John Carter, University of Utah
Michel Dubois, University of Southern California
Babak Falsafi, Carnegie Mellon University
Liviu Iftode, University of Maryland (co-chair)
Vijay Karamcheti, New York University
Darrell Long, University of California at Santa Cruz
Chistine Morin, IRISA, France
Workshop Organizers
Ricardo Bianchini
Department of Computer Science
Rutgers University
Piscataway, NJ 08854-8019
E-mail: ricardob@cs.rutgers.edu
Liviu Iftode
Department of Computer Science
University of Maryland
College Park, MD 20742
E-mail: iftode@cs.umd.edu
Contact
Please, send any questions or comments about the workshop to
wc3@cs.rutgers.edu.
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HPCA-9
Call for Papers
Ninth International Symposium on High Performance
Computer Architecture
Anaheim, California. Feb. 8-12, 2003
http://www.cs.arizona.edu/hpca9/
Important Dates
Paper submission deadline : July 12, 2002
Workshop proposals due : July 12, 2002
Author Notification : Oct. 1, 2002
Camera ready copy due : Nov. 3, 2002
The International Symposium on High-Performance Computer Architecture
provides a high quality forum for scientists and engineers to present
their latest research findings in this rapidly changing field. Authors
are invited to submit full papers on all aspects of high-performance
computer architecture. Topics of interest include, but are not limited
to:
* Processor architectures
* Cache and memory architectures
* Parallel computer architectures
* Impact of VLSI scaling techniques
* Novel architectures for emerging applications
* Power-efficient architectures
* High-availability architectures
* High-performance I/O architectures
* Embedded and reconfigurable architectures
* Real-time architectures
* Interconnection networks and network interfaces
* Innovative hardware/software trade-offs
* Simulation and performance evaluation
* Benchmarking and measurements
Please check the following web site for paper submission information:
http://www.cs.arizona.edu/hpca9/
The submission should not exceed 6000 words. Papers that exceed the
length limit or that cannot be viewed using Adobe Acrobat Reader
(version 3.0 or higher) may not be reviewed. The official submission
deadline is July 12, 2002 (Midnight EST, USA). An automatic extension
of one week will be given without request. No further extensions will be
given. Papers may be submitted for blind review at the option of the
authors. Please indicate whether the paper is a student paper for best
student paper nominations. Please submit proposals for workshops to the
workshop chair by July 12, 2002.
Important Dates
Paper submission deadline : July 12, 2002
Workshop proposals due : July 12, 2002
Author Notification : Oct. 1, 2002
Camera ready copy due : Nov. 3, 2002
General Chairs
Nader Bagherzadeh, Univ. of California, Irvine
Laxmi N. Bhuyan, Univ. of California, Riverside
Steering Committee
Dharma P. Agrawal, Univ. of Cincinnati
Laxmi N. Bhuyan, Univ. of California, Riverside
Yale Patt, Univ. of Texas at Austin
Jean-Luc Gaudiot, Univ. of California, Irvine
Joel Emer, Intel
David Kaeli, Northeastern Univ.
Pen-Chung Yew, Univ. of Minnesota
David Lilja, Univ. of Minnesota
Program Chair
Rajiv Gupta, Univ. of Arizona
Program Committee
Todd Austin, Univ. of Michigan
Pradip Bose, IBM
Doug Burger, Univ. of Texas at Austin
Brad Calder, Univ. of California, San Diego
Dan Connors, Univ. of Colorado
Tom Conte, NC State Univ.
Darren Cronquist, HP Labs
Chita Das, Penn State Univ.
Sandhya Dwarkadas, Univ. of Rochester
Marius Evers, AMD
Kanad Ghose, SUNY Binghamton
Antonio Gonzalez, UPC, Barcelona
James Goodman, Univ. of Wisconsin
Wei-Chung Hsu, Univ. of Minnesota
Yiming Hu, Univ. of Cincinnati
Stephen Jenks, Univ. of California, Irvine
Steve Melvin, Zytek
Walid Najjar, Univ. of California, Riverside
Soner Onder, Michigan Technological Univ.
Santosh Pande, Georgia Tech
Sanjay Patel, UIUC
John Shen, Intel, MRL
Josep Torrellas, UIUC
Mateo Valero, UPC, Barcelona
Jie Wu, Florida Atlantic Univ.
Yuanyuan Yang, SUNY at Stony Brook
Local Arrangements Chair
Stephen Jenks, Univ. of California, Irvine
Workshop Chair
Walid Najjar, Univ. of California, Riverside
Publications Chair
Li-Shiuan Peh, Princeton University
Finance and Registration Chair
Nayla Nassif, Univ. of California, Irvine
Publicity Chair
Soner Onder, Michigan Technological Univ.
If you have any questions about HPCA-9, please do not hesitate to
contact soner@mtu.edu.
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HOT Chips 14
A Symposium on High-Performance Chips
August 18-20, 2002, Memorial Auditorium,
Stanford University, Palo Alto, California
ADVANCED PROGRAM
Hot Chips 14 brings together designers and architects of high-performance
chips, software, and systems. Presentations focus on up-to-the-minute real
developments. This symposium is the primary forum for engineers and researchers
to highlight their leading-edge designs. Three full days of tutorials and
technical sessions will keep you on top of the industry.
Sunday, August 18
-----------------------------
Morning Tutorial Semiconductor Process Roadmap Issues, Sematech
Afternoon Tutorial TBA
Monday, August 19
-----------------------------
Intel Microprocessors
* Intel McKinley HP
* An Analysis of the CPU2K Benchmarks on the McKinley Processor, HP
* Intel Xeon Processor and Hyper-Threading Technology, Intel
Keynote: Eric Schmidt CTO, Google
* TBA
Network Processors
* Benchmark Performance of the IBM PowerNP NP4GS3 Network Processor, IBM
* AMCCís 2nd Generation 5Gbps Network Processor, Applied Micro Circuits
Interconnect
* A 20Gb/s 0.13um CMOS Serial Link, Stanford
* Smarter Interconnects for Smarter Chips, Sonics
* Building High Performance Multi-processor Systems with JIO, Sun
Technology
* Integrated Cryptographic Hardware Engines on the zSeries Microprocessor, IBM
* How a processor can permute n bits in O(1) cycles, Princeton University
* Thoughtbeam Technology, Motorola
Systems on Chip I
* The RM9000 Family of Integrated Multiprocessor Devices, PMC-Sierra
* Alchemy Au1X100, AMD
Panel: Embedded Systems Software : Visions of the Future, John Mashey
Tuesday, August 20
-----------------------------
Potpourri
* The Atheros Chipset for 108 Mb/s Multi-Mode Wireless LANs, Atheros
* PipeRench, CMU
* GeForce4, Nvidia
Keynote: Tom Edwards, NASA
* Air Traffic Control
Digital Signal Processing
* A New Distributed DSP Architecture Based on the Intel IXS, Intel
* VASA, NTT
Switches
* Delivering On The Promise of Asynchronous Circuit Design, Fulcrum
* A Multi-Terabit Scalable Switch Fabric: Architecture and Challenges, IBM
* CMOS Crossbar, HKU
Systems on Chip II
* FirePath, Broadcom
* Calisto, Broadcom
* BCM1101 Ethernet Enterprise IP Phone Platform, Broadcom
AMD Hammer
* The AMD x86-64 ISA: Extending the x86 to 64-bits, AMD
* The AMD Hammer Processor Core, AMD
* Hammer Shared Memory Multi Processor Systems, AMD
This is a preliminary program; changes may occur.
Registration will begin at http://www.hotchips.org after June 1st.
For the most up-to-the-minute details on presentations and schedules,
and for information on registration, please check http://www.hotchips.org.
For registration help, email mailto://hotchips14@hotmail.com
For general questions, email mailto://info@hotchips.org
Sponsored by the Technical Committee on Microprocessors and Microcomputers
of the IEEE Computer Society
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