SIGARCH-MSG: Addendum to March 2002 Digest of SIGARCH Messages

["Mark D. Hill" <markhill@cs.wisc.edu>]

This is an addendum to the March 2002 Digest of SIGARCH Messages
(sigarch-mar02b), which includes a call left out of the original
digest due to my error:

* ISCA Workshop on Memory Performance Issues (WMPI 2002)
  Call for Papers: http://iacoma.cs.uiuc.edu/wmpi2002
  Submitted by Josep Torrellas <torrella@cs.uiuc.edu>

--Mark D. Hill
infodir_SIGARCH@acm.org
SIGARCH Information Director

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                         CALL FOR PAPERS

     *****************************************************************
       2ND ANNUAL WORKSHOP ON MEMORY PERFORMANCE ISSUES (WMPI 2002)
                 http://iacoma.cs.uiuc.edu/wmpi2002
     *****************************************************************

                    Held in conjunction with the
                  29th International Symposium on
                 Computer Architecture (ISCA 2002)

                  Anchorage, Alaska, May 25, 2002

Organizers:

  Haldun Hadimioglu, Polytechnic University, haldun@photon.poly.edu
  David Kaeli, Northeastern University, kaeli@ece.neu.edu
  Jeff Kuskin, Atheros Communications, jsk@atheros.com
  Ashwini Nanda, IBM TJ Watson Research Center, ashwini@us.ibm.com
  Josep Torrellas, University of Illinois at Urbana-Champaign, torrellas@cs.uiuc.edu

Topics:

  WMPI is a 1-day workshop that provides a forum for researchers and
  practitioners from academia and industry to discuss advances in computer
  technology, architecture, software systems, and algorithms that address the
  growing disparity between memory and CPU/network speeds. Hardware and software
  techniques that address this performance gap are equally welcome. We are
  particularly interested in new ideas. Work in early stages of development is
  encouraged. The workshop will also include one or more keynote speakers.

  Possible topics for papers include, but are not limited to:

  * Processors in memory
  * Cache hierarchy organization and coherence
  * RAM architecture and technology
  * Reconfigurable memory systems
  * Intelligent disks
  * Bus/interconnect architectures
  * Network memory
  * Compilation techniques
  * Speculation at the instruction or thread levels
  * Low-power design of memory hierarchies
  * Memory compression
  * Operating system memory management
  * Hardware and software fault tolerance of memory systems
  * Multiprocessing on a single chip
  * Software cache coherence
  * Virtual memory systems

Submissions:

  Please submit a 10-page paper for review by the committee. Authors of accepted
  papers will present their work. Proceedings containing all papers will be
  provided to all attendees.

  The deadline for submission is March 22, 2002. Send your paper, in PS or PDF,
  to David Kaeli or Josep Torrellas:

  David Kaeli
  Northeastern University
  kaeli@ece.neu.edu

  Josep Torrellas
  University of Illinois at Urbana-Champaign
  torrellas@cs.uiuc.edu

Important Dates:

  Papers due: March 22, 2002
  Notification to authors: April 5, 2002
  Final papers due: April 26, 2002


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