[Gems-users] L2 misses in MESI_CMP directory protocol

["abhisekpan@xxxxxxxxx" <abhisekpan@xxxxxxxxx>]

Hi,

I am simulating a CMP (single chip with a shared last level cache) using the MESI_CMP_Directory protocol. I was looking at how the cache misses are counted
in the MESI_CMP_directory-L2cache.sm files. These are the conditions when an L2 miss is registered.

Current State    Events
NP                 GETS, GETX
IS, ISS           GETS
SS                 GETS, GETX, UPGRADE
M                   GETs, GETX,
MT                 GETS, GETX

The relevant state descriptions are as follows:
stable states:
NP, desc="Not present in either cache";
SS, desc="L2 cache entry Shared, also present in one or more L1s";
M, desc="L2 cache entry Modified, not present in any L1s";
MT, desc="L2 cache entry Modified in a local L1, assume L2 copy stale";
transient states:
ISS, desc="L2 idle, got single L1_GETS, issued memory fetch, have not seen response yet";
IS, desc="L2 idle, got L1_GET_INSTR or multiple L1_GETS, issued memory fetch, have not seen response yet";

I am confused why misses are registered for cases when the L2 block is in M, MT, or SS states. M means the L2 has the value and owns it already, MT means some L1 cache has
exclusive ownership, which will supply the value. There is no off-chip access. The only time when there is an off-chip memory access (a_issueFetchToMemory) is when the L2 is in 
NP state. So I thought these are the only cases where we should count an L2 miss.

I am struggling to explain all these other cases where L2 miss is registered. Any ideas / explanation regarding this would be very helpful!

Thanks a lot!

-- 
Abhisek
Live Long and Prosper