Re: [Gems-users] How to collect multicore coherence traffic

[jianhual@xxxxxxxxxxxxxxxx]

Hi Aparna,

Thanks for your reply. The files in ruby/generated/MOESI... are created when compiling ruby,
so how can I add code in such files? Are there any other ways to collect the multicore cache
coherence traffic trace?

Where can I add codes in GEMS to collect such traces? Can somebody help me? Thanks very much!

Regards,
Jianhua
-----------------------------------------------------------------------------
>Hi,
>Directly adding in SLICC code is difficult. But if you can add in file in
>ruby/generated/MOESI... directory which gets created on compiling ruby.
>check L2 and L1 controllers files for more info.
>thanks,
>Aparna

------------------------------------------------------------------------------

> Hi All,
>
>     I am a newbie to GEMS. Now, I want to utilize GEMS framework to
> collect the cache coherence traffic of real applications running on a
> multicore platform. Imagine that I use the directory coherence
> protocol for a 16-core CMP with private L1 cache and shared L2 cache
> (NUCA-like). How can I collect the various on-chip traffic, such as
> the L2 read, L2 write and L1 invalidate, etc.
>     Where can I add codes in the GEMS to implement such function? In SLICC
> or somewhere?
>
>     Thanks in advance.
>
> Regards,
> Jianhua
>
>
>
>
> _______________________________________________
> Gems-users mailing list
> Gems-users@xxxxxxxxxxx
> https://lists.cs.wisc.edu/mailman/listinfo/gems-users
> Use Google to search the GEMS Users mailing list by adding
> "site:https://lists.cs.wisc.edu/archive/gems-users/";; to your search.
>
>
> --
> This message has been scanned for viruses and
> dangerous content by MailScanner, and is
> believed to be clean.
>