[Gems-users] x86 instruction fetch and stall

["Yoon, Man Ki" <mkyoon@xxxxxxxx>]

Hi,

 

I am doing some simulation with x86 target (with Simics 4.2 + GEMS).

Because x86 in Simics doesn’t allow instruction fetches to be stalled, I added the following line to ruby_operate in ruby.c as explained in another thread:

 

if (!g->may_stall) { return 0; }

 

 

But a problem is that, I would like to see how the instruction cache (L1I) could affect the unified L2 cache (I am using MOSI_SM_bcast). But L1I cache is never simulated with the above line. So my question is, is there any way to simulate instruction cache with 0 latency? Where should I modify to do so?   Any comment or suggestion will be very appreciated.

 

Thanks