[Gems-users] write access to shared L2 cache

[Amin Jadidi <amin.jadidi@xxxxxxxxx>]

Hi,

I have using GEMS ver 2 with SIMICS 3.29. I have experiencing some simulations on a CMP with 4 cores. I have been running PARSEC benchmark suite and have noticed that write access to different way of a typical set in shared L2 cache is not uniformly distributed. Indeed, the write accesses are frequently done on the 3-4 ways (among 16 ways) while the others met less accesses. By the way, I have some experiences with the SESC simulator where the simulator moves the most frequently accessed lines (now reside in for example way 10) to low indexed ways (for example 1 or 2) in order to improve simulation time. [In this case a set was modeled by linear arrays]. I want to know that anybody has any knowledge of the GEMS behavior. Do Gems act the same as SESC to decrease search time or not? I have to note that replacement policy is LRU and cache coherency protocol is the MOESI_CMP_directory.

tnx