Re: [Gems-users] save-caches/load-caches bug

[Javi Merino <merinocj@xxxxxxxxx>]

Byn Choi wrote:
> Hello,
> 
> I think I may have found a bug in the save-caches/load-caches mechanism.
> 
> Here, I'm assuming a single-chip multicore environment.
> 
> [...]
> 
> CacheMemory::recordCacheContents() has the line
> tr.addRecord(m_chip_ptr->getID(), m_cache[i][j].m_Address, Address 
> (0), ... );
> m_chip_ptr->getID() is the same for all the cores in the chip, i.e.  
> with single-chip multicore, this value is always 0.
> 
> [...]
> 
> Am I missing something here? Is there an option that should be set to  
> correct this behavior?

Hi Bin, at my university, we do the warmup part of the checkpoint with
the MOESI_SMP_directory protocol and g_PROCS_PER_CHIP set to 1.
Afterwards, we load the caches of single-chip multicores without
problems: the data goes to the caches of the different cores.

I think this is the correct way of doing it. Even if they are different
coherence protocols, the data in the cache should be mostly the same, if
your cache configurations are similar in size. After all, it is the most
recently used data.

That's my experience, but I'd like to know how do others in the list do
the save-caches part of the workload creation.

Regards,
Javi

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