In theory, they should be independent. AKA, in the 'simulation model', they happen more-or-less concurrently. It shouldn't "matter" in what order the actions are performed.
In practice, they are performed sequentially.
Regards,
Dan
2010/4/8 Ma Dafan <dafan_ma@xxxxxxxxxxx>
I have another problem: the actions called in transition, are performed sequentially by list order, or just concurrently?
2010/4/9, Ma Dafan <dafan_ma@xxxxxxxxxxx>:
Thx，Dan，I got it.
2010/4/9, Dan Gibson <degibson@xxxxxxxx>:
OLSX, desc="Owned with local sharers, chip is exclusive";
IFLOX, desc="Blocked, forwarded local GETS to local owner but chip is exclusive";
If an L1 issues a GETX to a line in state OLSX, the L2 is owning the line but there are other on-chip caches with a copy of the line (however, there aren't any off-chip copies of the line). However, since the L1 wants an /exclusive/ copy, the GETX cannot be directly serviced by the L2. The state transitions to IFLOX, while invalidations are sent to sharers (except the requestor, of course). The data is present in the L2, so it can be sent to the requestor (i.e., d_sendDataToL1GETX), bu the the requesting L1 does not have the block exclusively until ACKS are received from the other sharers.
In other words, the L2 can supply the data (the GET of the GETX), but not the exclusivity (the X of the GETX), so it is a 'miss'.
Regards,
Dan
Hi, there,
Recently I check in the the file "MOESI_CMP_directory-L2cache.sm" and find something I can not understand.
In the code section cited below, a uu_profileMiss action is called when a L1_getx access actually hit in my opinion.
So I'm confused about the action "uu_profileMiss", can anyone help me?
transition(OLSX, L1_GETX, IFLOX) {
i_allocateTBE;
s_recordGetXL1ID;
// count number of INVs needed that doesn't include requestor
h_countLocalSharersExceptRequestor;
// issue INVs to everyone except requestor
ee_issueLocalInvExceptL1Requestor;
d_sendDataToL1GETX
y_copyCacheStateToDir;
r_setMRU;
rr_deallocateL2CacheBlock;
uu_profileMiss; //why? why miss, is it a hit?
o_popL1RequestQueue;
}
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Regards!
Wang
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Regards!
Wang
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