Hi,
First I want to quote a text from $OPAL/design/report-1-31-00.txt:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Just a basic O-o-O Simulator
---- - ----- ----- ---------
Craig's out-of-order processor simulator consists of: a prefetch unit,
a branch predictor (branch target buffer), a "static" decoder, a
"dynamic" decoder, current processor state (incl. integer/fp/control
register files), a sequencer (i.e. main()), a scheduler
(i.e. reservation station), a buffer of in-flight instructions, a cache
hierarchy, and a data TLB. The typical hardware structures in an out-of-order
processor are classes in Craig's implementation.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
My question is how can I access the prefetch unit? Where it is? I
already have read GEMS powerpoint tutorial many times but nowhere in
that I found this unit. The only things I found are:
1) slide 63 that describe the fetch stage. It is useful however I
couldn't find the corresponding .C and .h files
2) slide 89 that is the file structure of Opal. The only thing that I
think is related is the "fetch" folder however there are only branch
predictor models: agree, fatpredict, gshare, igshare, indirect,
mlpredict, ras, regstate, storeset, tlstack, Yags.
Any additional info is greatly appreciated.
--
// Naderan *Mahmood;
|