Re: [Gems-users] MOSI_SMP_bcast Protocol Question

[Byn Choi <bynchoi1@xxxxxxxxxxxx>]

Jerry,

It looks to be that way. The corresponding SLICC code is much easier to read (protocols/MOSI_SMP_bcast-cache.sm:190), reprinted here.

bool isCacheTagPresent(Address addr) {                                                                                                                                                                           

    return (L2cacheMemory.isTagPresent(addr) || L1DcacheMemory.isTagPresent(addr) || L1IcacheMemory.isTagPresent(addr));                                                                                           

  }

I don't know much about the design of this particular protocol, so I can't definitively comment on why that's the case. But my guess would be that the protocol doesn't model the delays among internal structures of individual chips.

Byn

On Nov 16, 2009, at 4:30 AM, Jerry Lin wrote:

Thank you for your reply, but I'm still a little confused.

In generated/MOSI_SMP_bcast/L1Cache_isCacheTagPresent.C, it checks not only  L1DcacheMemory and L1IcacheMemory,

but also L1Cache_L2cacheMemory.

And L1Cache_getState.C uses this function to get the coherence state.

Does it mean that every time I search the cache for checking coherence state, it would search not only L1 cache but also L2 cache?

Best regards!

2009/11/13 Niket Agarwal <niketa@xxxxxxxxxxxxx>

Since MOSI_SMP_bcast has private L1 and L2, I think this just refers
to the L1/L2 cache structure.

On Nov 13, 2009, at 5:37 AM, Jerry Lin wrote:

> Hi,
> I am learning about the Slicc and trying to modify the
> MOSI_SMP_bcast protocol recently.
> I wonder what does "m_chip_ptr-
> >m_L1Cache_L2cacheMemory_vec[m_version]" mean?
> Does this indicate L2 cache? or something else?
> Any advice and tips will be appreciated! Thanks!
> Best regards!

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