Re: [Gems-users] Private L2 in a CMP...

[David Bonavila <david.bonavila@xxxxxxxxxxxxxxxxxx>]

I want to compare a 256KB shared L2 system with a 2 x 128KB private L2 system, so I need that the configuration of both systems are as similar as possible in order to obtain comparable results. Both with direct private 16KB L1 I/D caches.

So, my configurations are:


COMMON PARAMETERS:
DIRECTORY_CACHE_LATENCY: 6

NULL_LATENCY: 1
ISSUE_LATENCY: 2
CACHE_RESPONSE_LATENCY: 12
L2_RESPONSE_LATENCY: 6
L2_TAG_LATENCY: 6
L1_RESPONSE_LATENCY: 3
MEMORY_RESPONSE_LATENCY_MINUS_2: 158
DIRECTORY_LATENCY: 80
NETWORK_LINK_LATENCY: 1

COPY_HEAD_LATENCY: 4
ON_CHIP_LINK_LATENCY: 1
RECYCLE_LATENCY: 10
L2_RECYCLE_LATENCY: 5
TIMER_LATENCY: 10000
TBE_RESPONSE_LATENCY: 1

L1_REQUEST_LATENCY: 2
L2_REQUEST_LATENCY: 4
SINGLE_ACCESS_L2_BANKS: true
SEQUENCER_TO_CONTROLLER_LATENCY: 4


SHARED L2 SYSTEM:                   PRIVATE L2 SYSTEM:

protocol: MSI_MOSI_CMP_directory                protocol: MSI_MOSI_CMP_directory
g_PROCS_PER_CHIP: 2                             g_PROCS_PER_CHIP: 1
g_NUM_CHIPS: 1                                  g_NUM_CHIPS: 2

g_NUM_L2_BANKS_PER_CHIP: 2                      g_NUM_L2_BANKS_PER_CHIP: 1
g_NUM_MEMORIES_PER_CHIP: 2                      g_NUM_MEMORIES_PER_CHIP: 1


network: SIMPLE_NETWORK                         network: SIMPLE_NETWORK

topology: HIERARCHICAL_SWITCH                   topology: HIERARCHICAL_SWITCH

L1Cache-0 Network Latencies                     L1Cache-0 Network Latencies
  L1Cache-0 -> L1Cache-1 net_lat: 9               L1Cache-0 -> L1Cache-1 net_lat: 5

  L1Cache-0 -> L2Cache-0 net_lat: 9               L1Cache-0 -> Directory-0 net_lat: 5
  L1Cache-0 -> L2Cache-1 net_lat: 9               L1Cache-0 -> Directory-1 net_lat: 5
  L1Cache-0 -> Directory-0 net_lat: 9           

  L1Cache-0 -> Directory-1 net_lat: 9

L1Cache-1 Network Latencies                     L1Cache-1 Network Latencies
  L1Cache-1 -> L1Cache-0 net_lat: 9               L1Cache-1 -> L1Cache-0 net_lat: 5
  L1Cache-1 -> L2Cache-0 net_lat: 9               L1Cache-1 -> Directory-0 net_lat: 5
  L1Cache-1 -> L2Cache-1 net_lat: 9                 L1Cache-1 -> Directory-1 net_lat: 5
  L1Cache-1 -> Directory-0 net_lat: 9
  L1Cache-1 -> Directory-1 net_lat: 9

L2Cache-0 Network Latencies 

  L2Cache-0 -> L1Cache-0 net_lat: 9
  L2Cache-0 -> L1Cache-1 net_lat: 9
  L2Cache-0 -> L2Cache-1 net_lat: 9
  L2Cache-0 -> Directory-0 net_lat: 9
  L2Cache-0 -> Directory-1 net_lat: 9

L2Cache-1 Network Latencies

  L2Cache-1 -> L1Cache-0 net_lat: 9
  L2Cache-1 -> L1Cache-1 net_lat: 9
  L2Cache-1 -> L2Cache-0 net_lat: 9
  L2Cache-1 -> Directory-0 net_lat: 9
  L2Cache-1 -> Directory-1 net_lat: 9

Directory-0 Network Latencies                   Directory-0 Network Latencies

  Directory-0 -> L1Cache-0 net_lat: 9             Directory-0 -> L1Cache-0 net_lat: 5
  Directory-0 -> L1Cache-1 net_lat: 9             Directory-0 -> L1Cache-1 net_lat: 5
  Directory-0 -> L2Cache-0 net_lat: 9             Directory-0 -> Directory-1 net_lat: 5

  Directory-0 -> L2Cache-1 net_lat: 9
  Directory-0 -> Directory-1 net_lat: 9

Directory-1 Network Latencies                   Directory-1 Network Latencies
  Directory-1 -> L1Cache-0 net_lat: 9             Directory-1 -> L1Cache-0 net_lat: 5

  Directory-1 -> L1Cache-1 net_lat: 9             Directory-1 -> L1Cache-1 net_lat: 5
  Directory-1 -> L2Cache-0 net_lat: 9             Directory-1 -> Directory-0 net_lat: 5
  Directory-1 -> L2Cache-1 net_lat: 9

  Directory-1 -> Directory-0 net_lat: 9


Total_Chips: 1                                  Total_Chips: 2
L1Cache_L1IcacheMemory numberPerChip: 2         L1Cache_L1IcacheMemory numberPerChip: 1
  cache_size_Kbytes: 16                           cache_size_Kbytes: 16

L1Cache_L1DcacheMemory numberPerChip: 2         L1Cache_L1DcacheMemory numberPerChip: 1
  cache_size_Kbytes: 16                           cache_size_Kbytes: 16
L2Cache_L2cacheMemory numberPerChip: 2          L1Cache_L2cacheMemory numberPerChip: 1

  cache_size_Kbytes: 128                          cache_size_Kbytes: 128


So the question is: are both systems well configured for what I m trying to achieve??

Do you need to know any other parameter to determine if they are right or wrong??


Thanks!

2009/6/15 David Bonavila <david.bonavila@xxxxxxxxxxxxxxxxxx>

Ruby says "Non-CMP protocol should set g_PROCS_PER_CHIP to 1" when using a SMP protocol and g_PROCS_PER_CHIP greater than 1, so I guess I will have to set g_PROCS_PER_CHIP to 1 and g_NUM_PROCESSORS to 2 to model a 2-core CMP.

There are 3 SMP protocols, and the first two of them use a unified L2 cache, so can I only use MOESI_SMP_hammer??

Which network latency parameters should I set to have a good approach of a CMP using 2 chips??

Thank you!!

2009/6/15 David Bonavila <david.bonavila@xxxxxxxxxxxxxxxxxx>

OK, thanks.
I need to model a 2-core CMP with private L2 for each of the cores.
Then, how should I configure these parameters?? I guess it should be something like this:

ruby0.setparam g_PROCS_PER_CHIP 1
ruby0.setparam g_NUM_PROCESSORS 2

Is that right?? Should I set any other parameters or configuration??
I have read something about making a fast interconnect between chips. Do I need any of that??

Thank you again!!

2009/6/15 David Bonavila <david.bonavila@xxxxxxxxxxxxxxxxxx>

Hi.

I need to configure a CMP with a private L2 cache, and I would like to know which of these configs I should use:

1)
ruby0.setparam g_PROCS_PER_CHIP 1
ruby0.setparam g_NUM_PROCESSORS 2

2)
ruby0.setparam g_PROCS_PER_CHIP 2
ruby0.setparam g_NUM_PROCESSORS 2
ruby0.setparam_str g_CACHE_DESIGN PRIVATE_L2

3)
ruby0.setparam g_PROCS_PER_CHIP 1
ruby0.setparam g_NUM_PROCESSORS 2
ruby0.setparam_str g_CACHE_DESIGN PRIVATE_L2

As I want to simulate a CMP, I guess I should use config number 2, but I don't know if that is the right way to do what I want.
Does config number 1 (without the g_CACHE_DESIGN parameter) provide a private L2 cache??
Or is any of them acceptable and the result will be the same??

Thanks!!