| 
Hello list,
i am trying to simulate thread migration in multiprocessors using 
simics/gems. More specifically i am trying to change the mapping between 
the simics processors and the processors of ruby . I am running a 
solaris image with 4 processors. simics processor 1 is mapped to gems 
processor 2 and simics processor 2 is mapped to gems processor 1. the 
other two (processor 0 and 3) are left without any mappings. i have made 
the necessary changes in gems/ruby/SimicsDriver.C and 
gems/ruby/SimicsProcessor.C and with the use of ruby's debugger 
everything seems to work right (right instructions are fetched by the 
right processor as the mapping suggests, the use of the right sequencer, 
L1 cache etc) The problem shows up in my simple cache miss counting 
benchmark when i try to bind a thread at the first of the three 
processor sets i created, more specifically with the use of function 
pset_bind. The processor in this set after some cycles of execution 
seems to be waiting for an interrupt that never comes and to be more 
specific in the simics terminal after manual break the following message 
is shown for processor 1 "Pending trap (0x60) Interrupt_Vector". Does 
anyone know what is going on here??? Are there any other changes that 
should be made in ruby's source code???? Thanks, 
Konstantinos
 |