[Gems-users] on parameter REMOVE_SINGLE_CYCLE_DCACHE_FAST

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Date:	Fri, 24 Oct 2008 10:41:04 -0700
From:	Xiang Xiao <xiaox@xxxxxxxxxx>
Subject:	[Gems-users] on parameter REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH and L1 cache stat

Hi,

I am using MSI_MOSI_CMP_directory protocol and Gems2.1/Simics 3 on a2-processor x86 target. When REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH is setto true, all L1I and L1D cache stats are zeors. WhenREMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH is set to false, I have L1D stats.Can anyone explain why Gems omit L1 stat whenREMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH is set to true?


Thanks a lot.

Xiang

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Today's Topics:

   1. Re: SLICC: explanation for deallocating certain blocks
      (Fuad Tabba)
   2. GEMS is not using signature filters (Ricardo Quislant del Barrio)
   3. Re: GEMS is not using signature filters (Luke Yen)
   4. Re: GEMS is not using signature filters
      (Ricardo Quislant del Barrio)
   5. Re: GEMS is not using signature filters (Luke Yen)
   6. Re: GEMS is not using signature filters
      (Ricardo Quislant del Barrio)
   7. SLICC question (Lois Orosa Nogueira)
   8. Having more than one cache request go out	simultaniously per
      processor (Fuad Tabba)
   9. Re: Having more than one cache request go out	simultaniously
      per processor (Dan Gibson)
  10. Re: Having more than one cache request go out	simultaniously
      per processor (Fuad Tabba)
  11. Re: SLICC question (Mike Marty)
  12. Re: Having more than one cache request go out	simultaniously
      per processor (Dan Gibson)


----------------------------------------------------------------------

Message: 1
Date: Thu, 23 Oct 2008 07:38:51 +1300
From: "Fuad Tabba" <fuad@xxxxxxxxxxxxxxxxx>
Subject: Re: [Gems-users] SLICC: explanation for deallocating certain
	blocks
To: "Gems Users" <gems-users@xxxxxxxxxxx>
Message-ID:
	<909c265f0810221138t7542f60bl81b7edf67a0a95bd@xxxxxxxxxxxxxx>
Content-Type: text/plain; charset="iso-8859-1"

I see... Thanks Luke!

Cheers,
/fuad


On Thu, Oct 23, 2008 at 4:42 AM, Luke Yen <lyen@xxxxxxxxxxx> wrote:

  Yes, it looks like it is safe to remove the ff_deallocateL1CacheBlock
actions.  At some point in the state transition setState() gets called and
it calls changePermission() in CacheMemory.h to change the state to
Invalid.

   Luke

On Wed, 22 Oct 2008, Fuad Tabba wrote:

Hi,

Looking at the SLICC coherence protocol file
MESI_CMP_filter_directory-L1cache.sm (the one used for LogTM-SE and

ATMTP) ,

I notice that   transition(IS_S, Nack_all, I) transition(IS_E, Nack_all,

I)

transition(IM_M, Nack_all, I): all of these perform a
ff_deallocateL1CacheBlock . What's the reasoning behind deallocating the
cache block there? Does it matter if the cacheblock doesn't get

deallocated,

I mean its state will still be I after all, and it's not really not

present,

it's just invalid...

Thanks.

Cheers,
/fuad

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Message: 2
Date: Thu, 23 Oct 2008 13:33:14 +0200
From: Ricardo Quislant del Barrio <quislant@xxxxxxxxx>
Subject: [Gems-users] GEMS is not using signature filters
To: gems-users@xxxxxxxxxxx
Message-ID: <490060FA.8080808@xxxxxxxxx>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed

Hi,

I'm simulating a benchmark with Simics 3.0.31 and GEMS 2.1. Everythingis going ok. There'sno errors, but it seems like GEMS is not using signature filters asstats show the following:

xact_read_set_size_dist: [binsize: 1 max: 0 count: 4096 average: 0 |standard deviation: 0 | 4096 ]xact_write_set_size_dist: [binsize: 1 max: 0 count: 4096 average: 0| standard deviation: 0 | 4096 ]

GEMS is counting the number of transactions but these transactions don'tinsert anything in the filters.


These are some parameters I set:

XACT_MEMORY: true
XACT_ENABLE_TOURMALINE: false
XACT_NUM_CURRENT: 0
XACT_LAST_UPDATE: 0
XACT_ISOLATION_CHECK: true
PERFECT_FILTER: false
READ_WRITE_FILTER: H3_1024_4_Regular
PERFECT_VIRTUAL_FILTER: true
VIRTUAL_READ_WRITE_FILTER: Perfect_
PERFECT_SUMMARY_FILTER: true
SUMMARY_READ_WRITE_FILTER: Perfect_
XACT_EAGER_CD: true
XACT_LAZY_VM: false
XACT_CONFLICT_RES: BASE
XACT_VISUALIZER: false
XACT_COMMIT_TOKEN_LATENCY: 0
XACT_NO_BACKOFF: false
XACT_LOG_BUFFER_SIZE: 0


Thanks


------------------------------

Message: 3
Date: Thu, 23 Oct 2008 09:25:35 -0500 (CDT)
From: Luke Yen <lyen@xxxxxxxxxxx>
Subject: Re: [Gems-users] GEMS is not using signature filters
To: Gems Users <gems-users@xxxxxxxxxxx>
Message-ID: <Pine.LNX.4.64.0810230923120.15361@xxxxxxxxxxxxxxxxxxxx>
Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed

Can you check whether there are any stats printed out for the "xactCommit" section? This lists each static XID and average stats (i.e.,read/write set lines, latency, aborts, etc.)

The stats you list below are independent of imperfect orperfect signatures, and should be nonzero even for Perfect signatures.


    Luke

On Thu, 23 Oct 2008, Ricardo Quislant del Barrio wrote:

Hi,
I'm simulating a benchmark with Simics 3.0.31 and GEMS 2.1. Everything
is going ok. There's
no errors, but it seems like GEMS is not using signature filters as
stats show the following:

xact_read_set_size_dist: [binsize: 1 max: 0 count: 4096 average:     0 |
standard deviation: 0 | 4096 ]
xact_write_set_size_dist: [binsize: 1 max: 0 count: 4096 average:     0
| standard deviation: 0 | 4096 ]

GEMS is counting the number of transactions but these transactions don't
insert anything in the filters.

These are some parameters I set:

XACT_MEMORY: true
XACT_ENABLE_TOURMALINE: false
XACT_NUM_CURRENT: 0
XACT_LAST_UPDATE: 0
XACT_ISOLATION_CHECK: true
PERFECT_FILTER: false
READ_WRITE_FILTER: H3_1024_4_Regular
PERFECT_VIRTUAL_FILTER: true
VIRTUAL_READ_WRITE_FILTER: Perfect_
PERFECT_SUMMARY_FILTER: true
SUMMARY_READ_WRITE_FILTER: Perfect_
XACT_EAGER_CD: true
XACT_LAZY_VM: false
XACT_CONFLICT_RES: BASE
XACT_VISUALIZER: false
XACT_COMMIT_TOKEN_LATENCY: 0
XACT_NO_BACKOFF: false
XACT_LOG_BUFFER_SIZE: 0


Thanks
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------------------------------

Message: 4
Date: Thu, 23 Oct 2008 16:58:03 +0200
From: Ricardo Quislant del Barrio <quislant@xxxxxxxxx>
Subject: Re: [Gems-users] GEMS is not using signature filters
To: gems-users@xxxxxxxxxxx
Message-ID: <490090FB.2040104@xxxxxxxxx>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed

Ok, here it is:

------- xact Commit Stats by XID --------

xact_stats id: 1 count: 4096 Cycles: 24431.6 Instr: 10185.4ReadSet: 0 WriteSet: 0 LoadMiss: 125.653 StoreMiss: 46.6521Retry Count: 0


"xact stats id" is 1 because I've set every BEGIN_TRANSACTION(id) with id=1.

I've tested the checkpoint in an older GEMS installation (GEMS 2.0 andSIMICS 3.0.29) and it runs perfectly.I inserted debugging couts inside H3BloomFilter::set,TransactionIsolationManager::addToWriteSetFilter, and

others, and nothing was shown.




------------------------------

Message: 5
Date: Thu, 23 Oct 2008 11:04:11 -0500 (CDT)
From: Luke Yen <lyen@xxxxxxxxxxx>
Subject: Re: [Gems-users] GEMS is not using signature filters
To: Gems Users <gems-users@xxxxxxxxxxx>
Message-ID: <Pine.LNX.4.64.0810231103340.15361@xxxxxxxxxxxxxxxxxxxx>
Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed

Can you also let us know if this is still a problem if Perfectsignatures are used?


    Luke


On Thu, 23 Oct 2008, Ricardo Quislant del Barrio wrote:

Ok, here it is:

------- xact Commit Stats by XID --------
xact_stats id: 1 count:    4096 Cycles: 24431.6 Instr: 10185.4
ReadSet:       0 WriteSet:       0 LoadMiss: 125.653 StoreMiss: 46.6521
Retry Count:       0

"xact stats id" is 1 because I've set every BEGIN_TRANSACTION(id) with id=1.
I've tested the checkpoint in an older GEMS installation (GEMS 2.0 and
SIMICS 3.0.29) and it runs perfectly.
I inserted debugging couts inside H3BloomFilter::set,
TransactionIsolationManager::addToWriteSetFilter, and
others, and nothing was shown.


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------------------------------

Message: 6
Date: Thu, 23 Oct 2008 18:32:15 +0200
From: Ricardo Quislant del Barrio <quislant@xxxxxxxxx>
Subject: Re: [Gems-users] GEMS is not using signature filters
To: gems-users@xxxxxxxxxxx
Message-ID: <4900A70F.1000109@xxxxxxxxx>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed

Yes indeed. It is a problem.

GEMS detects beginnings and endings of transactions but loads and storesare not labeled as

 CacheRequestType_LD/ST_XACT.

Maybe new version of Simics is the problem. This is printed out onsimulation:


### Executing "instruction-fetch-mode instruction-fetch-trace"

[cpu0 info] Note that on this cpu, instruction-fetch-trace isimplemented using instruction-cache-access-trace with a suitable cacheline size.[cpu1 info] Note that on this cpu, instruction-fetch-trace isimplemented using instruction-cache-access-trace with a suitable cacheline size.




------------------------------

Message: 7
Date: Thu, 23 Oct 2008 19:03:04 +0200
From: Lois Orosa Nogueira <lois.orosa@xxxxxx>
Subject: [Gems-users] SLICC question
To: Gems Users <gems-users@xxxxxxxxxxx>
Message-ID: <4900AE48.1010800@xxxxxx>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed

Hi list,

Is it posible to change the state of two diferent cache blocks at thesame time in a single cache request with a single trigger??

Thanks
Lois

------------------------------

Message: 8
Date: Fri, 24 Oct 2008 09:48:29 +1300
From: "Fuad Tabba" <fuad@xxxxxxxxxxxxxxxxx>
Subject: [Gems-users] Having more than one cache request go out
	simultaniously per processor
To: "Gems Users" <gems-users@xxxxxxxxxxx>
Message-ID:
	<909c265f0810231348gab80f3bl75f29694bc5b78af@xxxxxxxxxxxxxx>
Content-Type: text/plain; charset="iso-8859-1"

Hi,

In the process of diving into GEMS and understanding it thoroughly, I was
wondering if it is possible to issue more than one cache request at a time,
by the same processor, for different locations. If I understand the GEMS
code, it seems that there can be up to g_SEQUENCER_OUTSTANDING_REQUESTS
outstanding issued requests per processor? Is that right?

In practice, from looking at the code, I've only seen that happen in writing
a log, where a store GetX request would be issued for both the location and
the log entry itself.

This could be useful for prefeching items that might be needed soon...

Any ideas? Caveats that I should be aware of?

Thanks.

Cheers,
/fuad
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Message: 9
Date: Thu, 23 Oct 2008 15:57:53 -0500
From: "Dan Gibson" <degibson@xxxxxxxx>
Subject: Re: [Gems-users] Having more than one cache request go out
	simultaniously per processor
To: "Gems Users" <gems-users@xxxxxxxxxxx>
Message-ID:
	<e377c96e0810231357u4ed559adn6c81c7e4d57adb09@xxxxxxxxxxxxxx>
Content-Type: text/plain; charset="iso-8859-1"

This is not currently possible when executing only with Ruby, as Simics
models 'in-order' cores. When running with Opal, you should occasionally
observe multiple accesses per cycle from the same core.

Regards,
Dan

On Thu, Oct 23, 2008 at 3:48 PM, Fuad Tabba <fuad@xxxxxxxxxxxxxxxxx> wrote:

Hi,

In the process of diving into GEMS and understanding it thoroughly, I was
wondering if it is possible to issue more than one cache request at a time,
by the same processor, for different locations. If I understand the GEMS
code, it seems that there can be up to g_SEQUENCER_OUTSTANDING_REQUESTS
outstanding issued requests per processor? Is that right?

In practice, from looking at the code, I've only seen that happen in
writing a log, where a store GetX request would be issued for both the
location and the log entry itself.

This could be useful for prefeching items that might be needed soon...

Any ideas? Caveats that I should be aware of?

Thanks.

Cheers,
/fuad

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