Re: [Gems-users] Having more than one cache request go out simultaniously per processor

["Fuad Tabba" <fuad@xxxxxxxxxxxxxxxxx>]

I see what you're saying. Thanks Dan.

Cheers,
/fuad

On Fri, Oct 24, 2008 at 10:47 AM, Dan Gibson <degibson@xxxxxxxx> wrote:

This is an exception for LogTM in general. The current implementation of logging issues another GetX in the same cycle as the store itself. What I meant to imply is that the single-outstanding-request behavior of the Simics processor is basically fixed -- features implemented inside Ruby can do as they please, naturally.

Regards,
Dan

On Thu, Oct 23, 2008 at 4:40 PM, Fuad Tabba <fuad@xxxxxxxxxxxxxxxxx> wrote:

Thanks Dan.

But looking at the code for LogTM-SE, TransactionSimicsProcessor::generateLogRequest, which does send out a cache request to store the log entry, is issued at the same time (same cycle, in fact, same function call tree) as SimicsProcessor::makeRequest -> Sequencer::makeRequest -> Sequencer::doRequest, which issues a cache request for the inplace store.

So, if my understand is correct, it does seem that LogTM-SE at certain times issue two store cache requests simulatiously, and the hitCallback functions have the mechanisms in place to detect two callbacks triggerred by the same store; TransactionSimicsProcessor::completedMemRef keeps track of m_outstandingXactStoreRefCount , which would be set to 2 in the case of two cache requests sent for a LogTM store.

This seems to indicate that it might be possible in ruby, without running opal, to issue more than one cache request at a time.

Am I missing something in the code? Or is this case an exception made just for LogTM-SE? If it is an exception for LogTM-SE, is there a reason why such an exception can't be made in other contexts?

Thanks again Dan.

Cheers,
/fuad

On Fri, Oct 24, 2008 at 9:57 AM, Dan Gibson <degibson@xxxxxxxx> wrote:

This is not currently possible when executing only with Ruby, as Simics models 'in-order' cores. When running with Opal, you should occasionally observe multiple accesses per cycle from the same core.

Regards,
Dan

On Thu, Oct 23, 2008 at 3:48 PM, Fuad Tabba <fuad@xxxxxxxxxxxxxxxxx> wrote:

Hi,

In the process of diving into GEMS and understanding it thoroughly, I was wondering if it is possible to issue more than one cache request at a time, by the same processor, for different locations. If I understand the GEMS code, it seems that there can be up to g_SEQUENCER_OUTSTANDING_REQUESTS outstanding issued requests per processor? Is that right?

In practice, from looking at the code, I've only seen that happen in writing a log, where a store GetX request would be issued for both the location and the log entry itself.

This could be useful for prefeching items that might be needed soon...

Any ideas? Caveats that I should be aware of?

Thanks.

Cheers,
/fuad

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