Re: [Gems-users] MOSI-SMP-directory-1level

["Carole-Jean Wu" <carolewu@xxxxxxxxxxxxx>]

Hello Mike,

Is it L1 or L2 by the naming convention in this protocol?


Thanks alot,
Carole

On Mon, Mar 10, 2008 at 11:48 PM, Mike Marty <mike.marty@xxxxxxxxx> wrote:

If you look at the -cache.sm file, there is indeed only one CacheMemory object in each cache controller.  So there is only one cache level.  There must be a glitch in the stats for this protocol. 

--Mike

On Mon, Mar 10, 2008 at 1:58 PM, Carole-Jean Wu <carolewu@xxxxxxxxxxxxx> wrote:

Hello GEMS-users,

I am using MOSI_SMP_directory_1level protocol which assumes each node consists of a processor, private L1, private L2, and Memory/Directory controller. The SMP protocols can be used to model a CMP with private caches. Both the L1 and L2 caching is implemented in a single controll.

(MOSI_SMP_bcast_1level and MOSI_SMP_directory_1level Description: Similar to MOSI_SMP_bcast and MOSI_SMP_directory except that each processor has a single unified cache)

My interpretation of the protocol is that each processor has one level private cache, then misses in the cache do to main memory directory.

However, when I look at the ruby0.dump-stats file, the numerical data for L1D nor L1I are both 0 (with breakdown), and L2 data is non-zero (without breakdown) It seems like the 1 level cache is L2 and it is unified, shared among all processors.

Is this true? Then it is in conflict to the protocol description.


Thanks in advance for any help,
Carole

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