Re: [Gems-users] How to configure a shared L2 cache beyond single chip?

["Mike Marty" <mike.marty@xxxxxxxxx>]

On Mon, Jun 2, 2008 at 1:07 PM, Lide Duan <leaderduan@xxxxxxxxx> wrote:
> I found from GEMS wiki that those two-level CMP protocols (e.g.
> MOESI_CMP_directory, MS_MOSI_CMP_directory, MOESI_CMP_token, etc) assume a
> shared L2 cache *within one chip*. Does that mean there is no chance for a
> processor on chip0 to access some L2 cache bank on chip1 (assuming a
> two-chip CMP)?
>
> If I want to simulate a multi-chip CMP system which has a shared L2 cache
> among all the chips, i.e. the processors can access L2 banks on other chips,
> how should I configure Ruby? Does it make sense that all the processors are
> set within one chip (so that the whole L2 cache is shared in the protocol)
> but the network file (using FILE_SPECIFIED topology) is specified in a way
> that some differences exist between "the same chip" and "different chips",
> e.g. larger latency and lower bandwidth for the links connected between
> different chips, ?
>

Well in a multiple-chip system, a processor can access the L2 one a
different chip via the cache coherence protocol.

If you really want to logically share a single L2 cache across chips,
such that there is only 1 copy of the data stored in an L2 cache, just
configure any of the protocols with PROCS_PER_CHIP set to the total
number of processors.  Then define the topology in a FILE_SPECIFIED
network such that going to an L2 bank "off-chip" simply passes over
slower links.

--Mike


> Any suggestion is appreciated. Thanks,
> Lide
>
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